CY7C67300-100AXI Cypress Semiconductor Corp, CY7C67300-100AXI Datasheet - Page 29

• Manufacturer Part Number: CY7C67300-100AXI
• Description: IC USB HOST/PERIPH CNTRL 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-Host™r
• Type: Host Programmable Embedded USBr

Specifications of CY7C67300-100AXI

• Package / Case: 100-LQFP
• Applications: USB Host/Peripheral Controller
• Core Processor: CY16
• Program Memory Type: ROM (8 kB)
• Controller Series: CY7C673xx
• Ram Size: 16K x 8
• Interface: SPI Serial, USB, HPI
• Number Of I /o: 32
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current: 80 mA
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY4640 - KIT MASS STORAGE REF DESIGNCY3663 - KIT DEV EZ-OTG/EZ-HOST
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-1865; CY7C67300-100AXI

Port A SOF/EOP Enable (Bit 0)
The Port A SOF/EOP Enable bit is only applicable in host mode.
In device mode this bit must be written as ‘0’. In host mode this
bit enables or disables SOFs or EOPs for Port A. Either SOFs or
EOPs are generated depending on the LOA bit in the USB n
Control register when Port A is active.
1: Enable SOFs or EOPs
0: Disable SOFs or EOPs
USB Host Only Registers
There are twelve sets of dedicated registers for USB host only operation. Each set consists of two identical registers (unless otherwise
noted), one for Host Port 1 and one for Host Port 2. These register sets are covered in this section and summarized in
Table 47. USB Host Only Register
Host n Control Register [R/W]
■
■
Table 48. Host n Control Register
Register Description
The Host n Control register allows high level USB transaction
control.
Document #: 38-08015 Rev. *J
Host n Control Register
Host n Address Register
Host n Count Register
Host n Endpoint Status Register
Host n PID Register
Host n Count Result Register
Host n Device Address Register
Host n Interrupt Enable Register
Host n Status Register
Host n SOF/EOP Count Register
Host n SOF/EOP Counter Register
Host n Frame Register
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Host 1 Control Register 0xC080
Host 2 Control Register 0xC0A0
Preamble
Enable
R/W
15
0
7
0
-
Register Name
Sequence
Select
R/W
14
0
6
0
-
Enable
Sync
R/W
13
0
5
0
-
Enable
R/W
ISO
12
0
4
0
-
Reserved
0xC080/0xC0A0
0xC082/0xC0A2
0xC084/0xC0A4
0xC086/0xC0A6
0xC088/0xC0A8
0xC088/0xC0A8
0xC08C/0xC0AC
0xC090/0xC0B0
0xC096/0xC0B6
0xC086/0xC0A6
0xC092/0xC0B2
0xC094/0xC0B4
Reserved
Write all reserved bits with ’0’.
Preamble Enable (Bit 7)
The Preamble Enable bit enables or disables the transmission of
a preamble packet before all low-speed packets. Set this bit only
when communicating with a low-speed device.
1: Enable Preamble packet
0: Disable Preamble packet
Address (Host 1/Host 2)
11
0
3
0
-
-
Reserved
10
0
2
0
-
-
9
0
1
0
-
-
CY7C67300
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
W
R
R
R
R
Enable
Page 29 of 99
R/W
Arm
Table
8
0
0
0
-
47.
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