CY7C67300-100AXI Cypress Semiconductor Corp, CY7C67300-100AXI Datasheet - Page 28

• Manufacturer Part Number: CY7C67300-100AXI
• Description: IC USB HOST/PERIPH CNTRL 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-Host™r
• Type: Host Programmable Embedded USBr

Specifications of CY7C67300-100AXI

• Package / Case: 100-LQFP
• Applications: USB Host/Peripheral Controller
• Core Processor: CY16
• Program Memory Type: ROM (8 kB)
• Controller Series: CY7C673xx
• Ram Size: 16K x 8
• Interface: SPI Serial, USB, HPI
• Number Of I /o: 32
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current: 80 mA
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY4640 - KIT MASS STORAGE REF DESIGNCY3663 - KIT DEV EZ-OTG/EZ-HOST
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-1865; CY7C67300-100AXI

Port B D– Status (Bit 14)
The Port B D– Status bit is a read only bit that indicates the value
of DATA– on Port B.
1: D– is HIGH
0: D– is LOW
Port A D+ Status (Bit 13)
The Port A D+ Status bit is a read only bit that indicates the value
of DATA+ on Port A.
1: D+ is HIGH
0: D+ is LOW
Port A D– Status (Bit 12)
The Port A D– Status bit is a read only bit that indicates the value
of DATA– on Port A.
1: D– is HIGH
0: D– is LOW
LOB (Bit 11)
The LOB bit selects the speed of Port B.
1: Port B is set to low-speed mode
0: Port B is set to full-speed mode
LOA (Bit 10)
The LOA bit selects the speed of Port A.
1: Port A is set to low-speed mode
0: Port A is set to full-speed mode
Mode Select (Bit 9)
The Mode Select bit sets the SIE for host or device operation.
When set for device operation only one USB port is supported.
The active port is selected by the Port Select bit in the Host n
Count register.
1: Host mode
0: Device mode
Port B Resistors Enable (Bit 8)
The Port B Resistors Enable bit enables or disables the pull
up/pull down resistors on Port B. When enabled, the Mode
Select bit and LOB bit of this register set the pull up/pull down
resistors appropriately. When the Mode Select is set for Host
mode, the pull down resistors on the data lines (D+ and D–) are
enabled. When the Mode Select is set for Device mode, a single
pull up resistor on either D+ or D–, determined by the LOB bit, is
enabled. See
1: Enable pull up/pull down resistors
0: Disable pull up/pull down resistors
Port A Resistors Enable (Bit 7)
The Port A Resistors Enable bit enables or disables the pull
up/pull down resistors on Port A. When enabled, the Mode
Select bit and LOA bit of this register set the pull up/pull down
resistors appropriately. When the Mode Select is set for Host
mode, the pull down resistors on the data lines (D+ and D–) are
Document #: 38-08015 Rev. *J
Table 45
for details.
enabled. When the Mode Select is set for Device mode, a single
pull up resistor on either D+ or D–, determined by the LOA bit, is
enabled. See
1: Enable pull up/pull down resistors
0: Disable pull up/pull down resistors
Table 45. USB Data Line Pull Up and Pull Down Resistors
Port B Force D± State (Bits [6:5])
The Port B Force D± State field controls the forcing state of the
D+ D– data lines for Port B. This field forces the state of the Port
B data lines independent of the Port Select bit setting. See
Table 46
Port A Force D± State (Bits [4:3])
The Port A Force D± State field controls the forcing state of the
D+ D– data lines for Port A. This field forces the state of the Port
A data lines independent of the Port Select bit setting. See
Table 46
Table 46. Port A/B Force D± State
Suspend Enable (Bit 2)
The Suspend Enable bit enables or disables the suspend feature
on both ports. When suspend is enabled the USB transceivers
are powered down and cannot transmit or received USB packets
but can still monitor for a wakeup condition.
1: Enable suspend
0: Disable suspend
Port B SOF/EOP Enable (Bit 1)
The Port B SOF/EOP Enable bit is only applicable in host mode.
In device mode, this bit must be written as ‘0’. In host mode this
bit enables or disables SOFs or EOPs for Port B. Either SOFs or
EOPs are generated depending on the LOB bit in the USB n
Control register when Port B is active.
1: Enable SOFs or EOPs
0: Disable SOFs or EOPs
L0A/
Port A/B Force D± State
L0B
X
X
1
0
MSb
0
1
0
1
Select
for details.
for details.
Mode
X
1
0
0
Table 45
Resistors
LSb
Enable
Port n
0
0
1
1
0
1
1
1
for details.
Normal Operation
Force USB Reset, SE0 State
Force J-State
Force K-State
Pull up/Pull down on D+ and
D– Disabled
Pull down on D+ and
D– Enabled
Pull up on USB D– Enabled
Pull up on USB D+ Enabled
Function
Function
CY7C67300
Page 28 of 99
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