CY7C67300-100AXI Cypress Semiconductor Corp, CY7C67300-100AXI Datasheet - Page 17

• Manufacturer Part Number: CY7C67300-100AXI
• Description: IC USB HOST/PERIPH CNTRL 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-Host™r
• Type: Host Programmable Embedded USBr

Specifications of CY7C67300-100AXI

• Package / Case: 100-LQFP
• Applications: USB Host/Peripheral Controller
• Core Processor: CY16
• Program Memory Type: ROM (8 kB)
• Controller Series: CY7C673xx
• Ram Size: 16K x 8
• Interface: SPI Serial, USB, HPI
• Number Of I /o: 32
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current: 80 mA
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY4640 - KIT MASS STORAGE REF DESIGNCY3663 - KIT DEV EZ-OTG/EZ-HOST
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-1865; CY7C67300-100AXI

Bank Register [0xC002] [R/W]
Table 23. Bank Register
Register Description
The Bank register maps registers R0–R15 into RAM. The eleven MSBs of this register are used as a base address for registers
R0–R15. A register address is automatically generated by:
For example, if the Bank register is left at its default value of 0x0100, and R2 is read, then the physical address 0x0102 is read. Refer
to
Table 24. Bank Register Example
Address (Bits [15:4])
The Address field is used as a base address for all register addresses to start from.
Reserved
Write all reserved bits with ’0’.
Hardware Revision Register [0xC004] [R]
Table 25. Revision Register
Register Description
The Hardware Revision register is a read only register that indicates the silicon revision number. The first silicon revision is represented
by 0x0101. This number is increased by one for each new silicon revision.
Revision (Bits [15:0])
The Revision field contains the silicon revision number.
Document #: 38-08015 Rev. *J
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
1. Shifting the four LSBs of the register address left by 1.
2. ORing the four shifted bits of the register address with the twelve MSBs of the Bank register.
3. Forcing the LSB to zero.
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Table 24
for details.
RAM Location
Register
Bank
R/W
R/W
R14
15
15
R
X
R
X
0
7
0
7
...Address
R/W
R/W
14
14
R
X
R
X
0
6
0
6
R/W
R/W
13
13
R
X
R
X
0
5
0
5
0x000E << 1 = 0x001C
Hex Value
0x0100
0x011C
R/W
12
12
X
R
X
R
X
0
4
4
-
Revision...
...Revision
Address...
R/W
11
11
R
R
X
X
3
X
0
3
-
Reserved
R/W
10
10
R
R
X
X
2
X
0
2
-
0000 0001 0000 0000
0000 0001 0001 1100
0000 0000 0001 1100
Binary Value
R/W
R
X
R
X
X
9
1
9
0
1
-
CY7C67300
Page 17 of 99
R/W
R
X
R
X
X
8
0
8
1
0
-
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