CY7C67300-100AXI Cypress Semiconductor Corp, CY7C67300-100AXI Datasheet - Page 24

• Manufacturer Part Number: CY7C67300-100AXI
• Description: IC USB HOST/PERIPH CNTRL 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-Host™r
• Type: Host Programmable Embedded USBr

Specifications of CY7C67300-100AXI

• Package / Case: 100-LQFP
• Applications: USB Host/Peripheral Controller
• Core Processor: CY16
• Program Memory Type: ROM (8 kB)
• Controller Series: CY7C673xx
• Ram Size: 16K x 8
• Interface: SPI Serial, USB, HPI
• Number Of I /o: 32
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current: 80 mA
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY4640 - KIT MASS STORAGE REF DESIGNCY3663 - KIT DEV EZ-OTG/EZ-HOST
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-1865; CY7C67300-100AXI

Extended Page n Map Register [R/W]
■
■
Table 36. Extended Page n Map Register
Register Description
The Extended Page n Map register contains the Page n
high-order address bits. These bits are always appended to
accesses to the Page n Memory mapped space.
Address (Bits [15:0])
The Address field contains the high-order bits 28 to 13 of the
Page n address. The address pins [8:0] (Page n address [21:13])
Upper Address Enable Register [0xC038] [R/W]
Table 37. External Memory Control Register
Register Description
The Upper Address Enable register enables/disables the four
most significant bits of the external address A[18:15]. This
register defaults to having the Upper Address disabled. Note that
on power up, pins A[18:15] are driven high.
Document #: 38-08015 Rev. *J
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Extended Page 1 Map Register 0xC018
Extended Page 2 Map Register 0xC01A
R/W
R/W
15
15
X
0
7
0
X
7
-
-
R/W
R/W
14
14
X
0
6
0
X
6
-
-
Reserved
R/W
R/W
13
13
X
0
5
0
X
5
-
-
R/W
R/W
12
12
X
0
4
0
X
4
-
-
Address...
...Address
Reserved
reflect the content of this register when the CPU accesses the
address 0x8000-0x9FFF. For the SRAM mode, the address pin
on [4:0] (Page n address [17:13]) is used.
Set bit [8] (Page n address [21]) to ‘0’, so that Page n
reads/writes access external areas (SRAM, ROM or periph-
erals). nXMEMSEL is the external chip select for this space.
Upper Address Enable (Bit 3)
The Upper Address Enable bit enables/disables the four most
significant bits of the external address A[18:15].
1: Enable A[18:15] of the external memory interface for general
addressing.
0: Disable A[18:15], not available.
Reserved
Write all reserved bits with ’0’.
Address
Enable
Upper
R/W
R/W
R/W
11
11
0
3
0
X
3
0
-
R/W
R/W
10
10
0
X
2
0
X
2
-
Reserved
R/W
R/W
9
0
X
1
0
1
9
X
-
CY7C67300
Page 24 of 99
R/W
R/W
8
0
X
0
0
0
X
8
-
[+] Feedback