EP1SGX25CF672C6 Altera, EP1SGX25CF672C6 Datasheet - Page 121

• Manufacturer Part Number: EP1SGX25CF672C6
• Description: IC STRATIX GX FPGA 25KLE 672FBGA
• Manufacturer: Altera
• Series: Stratix® GXr

Specifications of EP1SGX25CF672C6

• Number Of Logic Elements/cells: 25660
• Number Of Labs/clbs: 2566
• Total Ram Bits: 1944576
• Number Of I /o: 455
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-FBGA
• Family Name: Stratix GX
• Number Of Logic Blocks/elements: 25660
• # I/os (max): 455
• Frequency (max): 5GHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 25660
• Ram Bits: 1944576
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 672
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Altera Corporation
February 2005
Table 4–13
Multiplier
The multiplier supports 9
DSP block supports eight possible 9
are four multiplier blocks available for multipliers larger than 9
but smaller than 18
multipliers larger than 18
The ability to have several small multipliers is useful in applications such
as video processing. Large multipliers greater than 18
for applications such as the mantissa multiplication of a single-precision
floating-point number.
The multiplier operands can be signed or unsigned numbers, where the
result is signed if either input is signed as shown in
sign_a and sign_b signals provide dynamic control of each operand’s
representation: a logic 1 indicates the operand is a signed number, a logic
0 indicates the operand is an unsigned number. These sign signals affect
all multipliers and adders within a single DSP block and you can register
them to match the data path pipeline. The multipliers are full precision
(that is, 18 bits for the 18-bit multiply, 36-bits for the 36-bit multiply, and
so on), regardless of whether sign_a or sign_b set the operands as
signed or unsigned numbers.
Parallel input
Shift register input
Table 4–13. Input Register Modes
Table 4–14. Multiplier Signed Representation
Register Input Mode
Unsigned
Unsigned
Data A
Signed
Signed
shows the summary of input register modes for the DSP block.
×
18 bits. There is one multiplier block available for
×
×
18 bits but smaller than or equal to 36
9-, 18
9
v
v
×
Unsigned
Unsigned
9
×
Data B
Signed
Signed
18-, or 36
Stratix GX Device Handbook, Volume 1
×
9-bit or smaller multipliers. There
×
18
36-bit multiplication. Each
v
v
×
18
Stratix GX Architecture
Table
×
18 bits are useful
Unsigned
Signed
Signed
Signed
Result
4–14. The
36
v
×
×
×
36 bits.
36
9 bits
4–55