EP4CE55F23C7 Altera, EP4CE55F23C7 Datasheet - Page 82

• Manufacturer Part Number: EP4CE55F23C7
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23C7

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

5–20
Figure 5–10. Cyclone IV E PLL Block Diagram
Notes to
(1) Each clock source can come from any of the four clock pins located on the same side of the device as the PLL.
(2) This is the VCO post-scale counter K.
(3) This input port is fed by a pin-driven dedicated GCLK, or through a clock control block if the clock control block is fed by an output from another
Cyclone IV Device Handbook, Volume 1
Clock inputs
from pins
GCLK
pfdena
PLL or a pin-driven dedicated GCLK. An internally generated global signal cannot drive the PLL.
(3)
Figure
4
5–10:
1
inclk0
inclk1
Figure 5–10
Cyclone IV E devices.
The VCO post-scale counter K is used to divide the supported VCO range by two. The
VCO frequency reported by the Quartus II software in the PLL summary section of
the compilation report takes into consideration the VCO post-scale counter value.
Therefore, if the VCO post-scale counter has a value of 2, the frequency reported is
lower than the f
Switchover
Clock
Block
÷n
activeclock
clkswitch
clkbad0
clkbad1
shows a simplified block diagram of the major components of the PLL of
VCO
specification specified in the
(Note 1)
PFD
LOCK
circuit
CP
Detector
Range
VCO
lock
LF
VCO
8
VCOOVRR
VCOUNDR
no compensation;
source-synchronous;
normal mode
÷2 (2)
ZDB mode
Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
Cyclone IV Device Datasheet
8
÷M
÷C0
÷C1
÷C2
÷C3
÷C4
© December 2010 Altera Corporation
output
mux
PLL
Cyclone IV PLL Hardware Overview
GCLKs
External clock output
GCLK networks
chapter.