EP4CE55F23C7 Altera, EP4CE55F23C7 Datasheet - Page 77

• Manufacturer Part Number: EP4CE55F23C7
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23C7

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
Clock Networks
GCLK Network Power Down
clkena Signals
© December 2010 Altera Corporation
f
Figure 5–6. Clock Control Blocks on Each Side of Cyclone IV E Device
Note to
(1) The left and right sides of the device have two DPCLK pins; the top and bottom of the device have four DPCLK pins.
You can disable a Cyclone IV device’s GCLK (power down) using both static and
dynamic approaches. In the static approach, configuration bits are set in the
configuration file generated by the Quartus II software, which automatically disables
unused GCLKs. The dynamic clock enable or disable feature allows internal logic to
control clock enable or disable the GCLKs in Cyclone IV devices.
When a clock network is disabled, all the logic fed by the clock network is in an
off-state, thereby reducing the overall power consumption of the device. This function
is independent of the PLL and is applied directly on the clock network, as shown in
Figure 5–1 on page
You can set the input clock sources and the clkena signals for the GCLK multiplexers
through the Quartus II software using the ALTCLKCTRL megafunction.
For more information, refer to the
Cyclone IV devices support clkena signals at the GCLK network level. This allows
you to gate-off the clock even when a PLL is used. Upon re-enabling the output clock,
the PLL does not need a resynchronization or re-lock period because the circuit gates
off the clock at the clock network level. In addition, the PLL can remain locked
independent of the clkena signals because the loop-related counters are not affected.
Figure 5–7
Figure 5–7. clkena Implementation
Figure
shows how to implement the clkena signal with a single register.
5–6:
5–10.
Clock Input Pins
clkena
Internal Logic
clkin
PLL Outputs
CDPCLK
DPCLK
ALTCLKCTRL Megafunction User
3 or 4
2 or 4
5
2
5
Blocks on Each Side
Five Clock Control
D
of the Device
Control
Q
Clock
Block
clkena_out
5
Cyclone IV Device Handbook, Volume 1
clk_out
GCLK
(Note 1)
Guide.
5–15