EP4CE55F23C7 Altera, EP4CE55F23C7 Datasheet - Page 215

• Manufacturer Part Number: EP4CE55F23C7
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23C7

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices
Configuration
Figure 8–25. JTAG Configuration of Multiple Devices Using a Download Cable (2.5, 3.0, and 3.3-V V
Pins)
Notes to
(1) Connect these pull-up resistors to the V
(2) Connect the nCONFIG and MSEL pins to support a non-JTAG configuration scheme. If you only use a JTAG configuration, connect the nCONFIG
(3) Pin 6 of the header is a V
(4) You must connect the nCE pin to GND or driven low for successful JTAG configuration.
(5) Power up the V
(6) Resistor value can vary from 1 k to 10 k..
© December 2010 Altera Corporation
Pin 1
10-Pin Male Header
Download Cable
pin to logic-high and the MSEL pins to GND. In addition, pull DCLK and DATA[0] to either high or low, whichever is convenient on your board.
MasterBlaster Serial/USB Communications Cable User
ByteBlaster II cables, this pin is connected to nCE when it is used for AS programming, otherwise it is a no connect.
to 2.5 V. Pin 4 of the header is a V
circuit boards, DC power supply, or 5.0 V from the USB cable. For this value, refer to the
Guide.
Figure
V
CCA
(5)
VIO
(3)
8–25:
(6)
V
1 kΩ
CC
CCA
V
of the ByteBlaster II, USB-Blaster, or ByteBlasterMV cable with a 2.5-V supply from V
CCA
(6)
When programming a JTAG device chain, one JTAG-compatible header is connected
to several devices. The number of devices in the JTAG chain is limited only by the
drive capability of the download cable. When four or more devices are connected in a
JTAG chain, Altera recommends buffering the TCK, TDI, and TMS pins with an
on-board buffer.
JTAG-chain device programming is ideal when the system contains multiple devices,
or when testing your system with JTAG BST circuitry.
show multi-device JTAG configuration.
For devices using 2.5-, 3.0-, and 3.3-V V
I/O inputs must maintain a maximum AC voltage of 4.1 V because JTAG pins do not
have the internal PCI clamping diodes to prevent voltage overshoot when using 2.5-,
3.0-, and 3.3- V V
2.5-V V
You can power up the V
IO
(2)
(2)
(2)
(2)
(2)
V
reference voltage for the MasterBlaster output driver. V
CCIO
10 kΩ
MSEL[ ]
(1)
nST A TUS
DATA[0]
DCLK
nCONFIG
nCEO
nCE (4)
TDI
CC
CCA
TMS
power supply for the MasterBlaster cable. The MasterBlaster cable can receive power from either 5.0- or 3.3-V
Cyclone IV Device
supply. For device using V
CCIO
TCK
CONF_DONE
supply of the bank in which the pin resides.
CCIO
TDO
V
supply. You must power up the V
CCIO
Guide. In the ByteBlasterMV cable, this pin is a no connect. In the USB-Blaster and
10 kΩ
(1)
CC
of the download cable with the supply from V
(2)
(2)
(2)
(2)
(2)
V
CCIO
10 kΩ
(1)
nST A TUS
DATA[0]
DCLK
nCONFIG
nCEO
nCE (4)
TDI
MSEL[ ]
TMS
Cyclone IV Device
CCIO
CCIO
TCK
CONF_DONE
of 1.2, 1.5 V, and 1.8 V, refer to
IO
must match the V
supply, you must refer to
TDO
MasterBlaster Serial/USB Communications Cable User
V
CCIO
10 kΩ
(1)
CC
Figure 8–25
(2)
(2)
(2)
CCA
(2)
(2)
CCA
V
of the download cable with a
CCIO
of the device. For this value, refer to the
. Third-party programmers must switch
Cyclone IV Device Handbook, Volume 1
10 kΩ
(1)
MSEL[ ]
nST A TUS
DATA[0]
DCLK
nCONFIG
nCEO
nCE (4)
TDI
TMS
Cyclone IV Device
CCIO
and
TCK
CONF_DONE
Powering the JTAG
Figure
Figure 8–26
Figure
TDO
CCIO
V
CCIO
8–25. All
.
10 kΩ
(1)
8–26.
8–49