EP4CE55F23C7 Altera, EP4CE55F23C7 Datasheet - Page 420

• Manufacturer Part Number: EP4CE55F23C7
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23C7

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

3–30
Figure 3–14. Option 2 for Receiver Core Clocking (Channel Reconfiguration Mode)
Note to
(1) Assuming channel 2 and 3 are running at the same data rate with rate matcher enabled and are reconfigured to another Basic or Protocol functional
Cyclone IV Device Handbook, Volume 2
mode with rate matching enabled.
Figure
3–14:
tx_clkout[0]
tx_clkout[1]
tx_clkout[2]
FPGA Fabric
Figure 3–14
channels of a transceiver block.
Option 3: Use the Respective Channel Receiver Core Clocks
■
■
Low-speed parallel clock
High-speed serial clock generated by the MPLL
Enable this option if you want the individual channel’s rx_clkout signal to
provide the read clock to its respective Receive Phase Compensation FIFO.
This option is typically enabled when the channel is reconfigured from a Basic or
Protocol configuration with or without rate matching to another Basic or Protocol
configuration with or without rate matching.
shows the respective tx_clkout of each channel clocking the respective
Transceiver Block
RX0
RX1
RX2 (1)
RX3 (1)
TX0
TX1
TX2 (1)
TX3 (1)
Chapter 3: Cyclone IV Dynamic Reconfiguration
© December 2010 Altera Corporation
MPLL
Dynamic Reconfiguration Modes