EP4CE55F23C7 Altera, EP4CE55F23C7 Datasheet - Page 191

• Manufacturer Part Number: EP4CE55F23C7
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23C7

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices
Configuration
Figure 8–8. Byte-Wide Multi-Device AP Configuration
Notes to
(1) Connect the pull-up resistors to the V
(2) Connect the pull-up resistor to the V
(3) The nCEO pin is left unconnected or used as a user I/O pin when it does not feed the nCE pin of another device.
(4) The MSEL pin settings vary for different configuration voltage standards and POR time. You must set the master device in AP mode and the slave
(5) The AP configuration ignores the WAIT signal during configuration mode. However, if you are accessing flash during user mode with user logic,
(6) Connect the repeater buffers between the Cyclone IV E master device and slave devices for DATA[15..0] and DCLK. All I/O inputs must
© December 2010 Altera Corporation
devices in FPP mode. To connect MSEL[3..0] for the master device in AP mode and the slave devices in FPP mode, refer to
page
you can optionally use the normal I/O to monitor the WAIT signal from the Numonyx P30 or P33 flash.
maintain a maximum AC voltage of 4.1 V. The output resistance of the repeater buffers must fit the maximum overshoot equation outlined in
“Configuration and JTAG Pin I/O Requirements” on page
Numonyx P30/P33 Flash
Figure
8–9. Connect the MSEL pins directly to V
8–8:
DQ[15:0]
A[24:1]
RST#
ADV#
WAIT
WE#
OE#
CLK
CE#
Byte-Wide Multi-Device AP Configuration
The simpler method for multi-device AP configuration is the byte-wide multi-device
AP configuration. In the byte-wide multi-device AP configuration, the LSB of the
DATA[7..0]pin from the flash and master device (set to the AP configuration
scheme) is connected to the slave devices set to the FPP configuration scheme, as
shown in
Word-Wide Multi-Device AP Configuration
The more efficient setup is one in which some of the slave devices are connected to the
LSB of the DATA[7..0]and the remaining slave devices are connected to the MSB of
the DATA[15..8]. In the word-wide multi-device AP configuration, the nCEO pin of
the master device enables two separate daisy chains of slave devices, allowing both
chains to be programmed concurrently, as shown in
GND
CCIO
10 kΩ
Figure
CCIO
V CCIO (1)
Buffers (6)
supply voltage of the I/O bank in which the nCE pin resides.
nCE
DCLK
nRESET
FLASH_nCE
nOE
nAVD
nWE
I/O (5)
DATA[15..0]
PADD[23..0]
supply of the bank in which the pin resides.
10 kΩ
Master Device
Cyclone IV E
CCA
8–8.
V CCIO (1)
or GND.
MSEL[3..0]
10 kΩ
V CCIO (1)
8–5.
nCEO
10 kΩ
V CCIO (2)
DQ[7..0]
(4)
Cyclone IV E Slave Device
nCE
DATA[7..0]
DCLK
MSEL[3..0]
nCEO
10 kΩ
V CCIO (2)
DQ[7..0]
Figure
(4)
Cyclone IV Device Handbook, Volume 1
Cyclone IV E Slave Device
nCE
DATA[7..0]
DCLK
8–9.
MSEL[3..0]
nCEO
Table 8–5 on
(4)
N.C. (3)
8–25