EP4CE55F23C7 Altera, EP4CE55F23C7 Datasheet - Page 117

• Manufacturer Part Number: EP4CE55F23C7
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23C7

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 6: I/O Features in Cyclone IV Devices
OCT Support
On-Chip Series Termination with Calibration
© December 2010 Altera Corporation
1
Cyclone IV devices support R
banks. The R
to the external 25- ±1% or 50- ±1% resistors connected to the RUP and RDN pins,
and dynamically adjusts the I/O buffer impedance until they match (as shown in
Figure
The R
the I/O buffer.
Figure 6–2. Cyclone IV Devices R
OCT with calibration is achieved using the OCT calibration block circuitry. There is
one OCT calibration block in each of I/O banks 2, 4, 5, and 7 for Cyclone IV E devices
and I/O banks 4, 5, and 7 for Cyclone IV GX devices. Each calibration block supports
each side of the I/O banks. Because there are two I/O banks sharing the same
calibration block, both banks must have the same V
calibration. If two related banks have different V
calibration block resides can enable OCT calibration.
Figure 6–10 on page 6–18
placement.
Each calibration block comes with a pair of RUP and RDN pins. When used for
calibration, the RUP pin is connected to V
50- ±1% resistor for an R
connected to GND through an external 25- ±1% or 50- ±1% resistor for an R
value of 25  or 50  , respectively. The external resistors are compared with the
internal resistance using comparators. The resultant outputs of the comparators are
used by the OCT calibration block to dynamically adjust buffer impedance.
During calibration, the resistance of the RUP and RDN pins varies.
S
6–2).
shown in
S
OCT calibration circuit compares the total impedance of the I/O buffer
Figure 6–2
Cyclone IV Device Family
Driver Series Termination
shows the top-level view of the OCT calibration blocks
S
OCT value of 25  or 50  , respectively. The RDN pin is
is the intrinsic impedance of the transistors that make up
S
S
OCT with Calibration
OCT with calibration in the top, bottom, and right I/O
V
GND
CCIO
R
R
S
S
CCIO
through an external 25- ±1% or
Z
CCIO
O
CCIO
, only the bank in which the
if both banks enable OCT
Receiving
Cyclone IV Device Handbook, Volume 1
Device
S
OCT
6–9