EP4CE55F23C7 Altera, EP4CE55F23C7 Datasheet - Page 200

• Manufacturer Part Number: EP4CE55F23C7
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23C7

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

8–34
Cyclone IV Device Handbook, Volume 1
After the first device completes configuration in a multi-device configuration chain,
its nCEO pin drives low to activate the nCE pin of the second device, which prompts
the second device to begin configuration. The second device in the chain begins
configuration in one clock cycle. Therefore, the transfer of data destinations is
transparent to the external host device. nCONFIG, nSTATUS, DCLK, DATA[0], and
CONF_DONE configuration pins are connected to every device in the chain. To ensure
signal integrity and prevent clock skew problems, configuration signals may require
buffering. Ensure that DCLK and DATA lines are buffered. All devices initialize and
enter user mode at the same time because all CONF_DONE pins are tied together.
If any device detects an error, configuration stops for the entire chain and you must
reconfigure the entire chain because all nSTATUS and CONF_DONE pins are tied
together. For example, if the first device flags an error on nSTATUS, it resets the chain
by pulling its nSTATUS pin low. This behavior is similar to a single device detecting
an error.
You can have multiple devices that contain the same configuration data in your
system. To support this configuration scheme, all device nCE inputs are tied to GND,
while the nCEO pins are left floating. nCONFIG, nSTATUS, DCLK, DATA[0], and
CONF_DONE configuration pins are connected to every device in the chain. To ensure
signal integrity and prevent clock skew problems, configuration signals may require
buffering. Ensure that the DCLK and DATA lines are buffered. Devices must be of the
same density and package. All devices start and complete configuration at the same
time.
Figure 8–15
receiving the same configuration data.
Figure 8–15. Multi-Device PS Configuration When Both Devices Receive the Same Data
Notes to
(1) You must connect the pull-up resistor to a supply that provides an acceptable input signal for all devices in the chain.
(2) The nCEO pins of both devices are left unconnected or used as user I/O pins when configuring the same
(3) The MSEL pin settings vary for different configuration voltage standards and POR time. To connect the MSEL pins,
(4) All I/O inputs must maintain a maximum AC voltage of 4.1 V. DATA[0] and DCLK must fit the maximum overshoot
(MAX II Device or
Microprocessor)
External Host
V
configuration data into multiple devices.
refer to
to V
outlined in
CC
ADDR
must be high enough to meet the V
CCA
Figure
Memory
or GND.
Table 8–3 on page
DATA[0]
Equation 8–1 on page
shows a multi-device PS configuration when both Cyclone IV devices are
8–15:
10 k
V
CCIO
8–8,
(1) V
10 k
Table 8–4 on page
CCIO
8–5.
Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices
GND
(1)
IH
specification of the I/O on the device and the external host.
Buffers (4)
Cyclone IV Master Device
CONF_DONE
nSTATUS
nCE
DATA[0] (4)
nCONFIG
DCLK (4)
8–8, and
MSEL[ ]
nCEO
Table 8–5 on page
(3)
N.C. (2)
© December 2010 Altera Corporation
8–9. Connect the MSEL pins directly
GND
Cyclone IV Slave Device
CONF_DONE
nSTATUS
nCE
DATA[0] (4)
nCONFIG
DCLK (4)
MSEL[ ]
nCEO
Configuration
N.C. (2)
(3)