EP4CE55F23C7 Altera, EP4CE55F23C7 Datasheet - Page 335

• Manufacturer Part Number: EP4CE55F23C7
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23C7

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 1: Cyclone IV Transceivers Architecture
Transceiver Functional Modes
Figure 1–55. Transceiver Channel Datapath and Clocking when Configured in GIGE Mode
Notes to
(1) Low-speed recovered clock.
(2) High-speed recovered clock.
(3) Optional rx_recovclkout port from CDR low-speed recovered clock is available for applications such as Synchronous Ethernet.
© December 2010 Altera Corporation
rx_recovclkout
rx_dataout
Fabric
FPGA
tx_datain
tx_clkout
Figure 1–55
(3)
:
The 1000 Base-X PHY is defined by IEEE 802.3 standard as an intermediate or
transition layer that interfaces various physical media with the media access control
(MAC) in a GbE system. The 1000 Base-X PHY, which has a physical interface data
rate of 1.25 Gbps consists of the PCS, PMA, and physical media dependent (PMD)
layers.
Figure 1–54. 1000 Base-X PHY in a GbE OSI Reference Model
Notes to
(1) CSMA/CD = Carrier-Sense Multiple Access with Collision Detection
(2) GMII = gigabit medium independent interface
Figure 1–55
GIGE mode.
Figure
Figure 1–54
Phase
Comp
FIFO
Rx
shows the transceiver channel datapath and clocking when configured in
1–54:
wr_clk
Tx Phase
Comp
FIFO
rd_clk
shows the 1000 Base-X PHY in LAN layers.
Logical Link Control (LLC) or other MAC client
Order-
Byte
ing
LAN CSMA/DC Layers
serializer
Byte
De-
MAC Control (Optional)
Reconcilation
Higher Layers
wr_clk
Byte Serializer
Medium
MAC
PMA
PMD
PCS
Transmitter Channel PCS
Decoder
8B/10B
rd_clk
Receiver Channel PCS
GMII
(2)
(1)
Match
FIFO
Rate
8B/10B Encoder
1000 Base-X PHY
Deskew
FIFO
Cyclone IV Device Handbook, Volume 2
(1)
Aligner
Word
Deserial-
Transmitter Channel PMA
Receiver Channel PMA
izer
Serializer
(2)
1–55
CDR
low-speed clock
high-speed
clock
CDR clock