EP4CE55F23C7 Altera, EP4CE55F23C7 Datasheet - Page 48

• Manufacturer Part Number: EP4CE55F23C7
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23C7

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

3–12
Figure 3–11. Cyclone IV Devices True Dual-Port Timing Waveform
Shift Register Mode
Cyclone IV Device Handbook, Volume 1
q_a (asynch)
q_b (asynch)
address_a
address_b
data_a
rden_a
wren_a
wren_b
rden_b
clk_a
clk_b
din-1
an-1
doutn-1
Cyclone IV devices M9K memory blocks can implement shift registers for digital
signal processing (DSP) applications, such as finite impulse response (FIR) filters,
pseudo-random number generators, multi-channel filtering, and auto-correlation and
cross-correlation functions. These and other DSP applications require local data
storage, traditionally implemented with standard flipflops that quickly exhaust many
logic cells for large shift registers. A more efficient alternative is to use embedded
memory as a shift register block, which saves logic cell and routing resources.
The size of a (w × m × n) shift register is determined by the input data width (w), the
length of the taps (m), and the number of taps (n), and must be less than or equal to
the maximum number of memory bits, which is 9,216 bits. In addition, the size of
(w × n) must be less than or equal to the maximum width of the block, which is 36 bits.
If you need a larger shift register, you can cascade the M9K memory blocks.
bn
din-1
din
an
doutn
din
b0
a0
dout0
a1
dout0
dout1
b1
a2
dout2
a3
Chapter 3: Memory Blocks in Cyclone IV Devices
dout3
dout1
b2
din4
a4
© November 2009 Altera Corporation
din4
din5
a5
dout2
din5
b3
din6
a6
Memory Modes