EP2C8T144I8N Altera, EP2C8T144I8N Datasheet - Page 42

IC CYCLONE II FPGA 8K 144-TQFP

EP2C8T144I8N

Manufacturer Part Number
EP2C8T144I8N
Description
IC CYCLONE II FPGA 8K 144-TQFP
Manufacturer
Altera
Series
Cyclone® IIr
Datasheet

Specifications of EP2C8T144I8N

Number Of Logic Elements/cells
8256
Number Of Labs/clbs
516
Total Ram Bits
165888
Number Of I /o
85
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
144-TQFP, 144-VQFP
Family Name
Cyclone® II
Number Of Logic Blocks/elements
8256
# I/os (max)
85
Frequency (max)
402.58MHz
Process Technology
90nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
8256
Ram Bits
165888
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
144
Package Type
TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2157

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Embedded Memory
2–30
Cyclone II Device Handbook, Volume 1
Memory Modes
Table 2–7
M4K memory blocks.
1
Single-port memory
Simple dual-port memory
Simple dual-port with mixed
width
True dual-port memory
True dual-port with mixed
width
Embedded shift register
ROM
FIFO buffers
Table 2–7. M4K Memory Modes
Memory Mode
Embedded Memory can be inferred in your HDL code or
directly instantiated in the Quartus II software using the
MegaWizard
summarizes the different memory modes supported by the
®
Plug-in Manager Memory Compiler feature.
M4K blocks support single-port mode, used when
simultaneous reads and writes are not required.
Single-port memory supports non-simultaneous
reads and writes.
Simple dual-port memory supports a
simultaneous read and write.
Simple dual-port memory mode with different
read and write port widths.
True dual-port mode supports any combination of
two-port operations: two reads, two writes, or one
read and one write at two different clock
frequencies.
True dual-port mode with different read and write
port widths.
M4K memory blocks are used to implement shift
registers. Data is written into each address
location at the falling edge of the clock and read
from the address at the rising edge of the clock.
The M4K memory blocks support ROM mode. A
MIF initializes the ROM contents of these blocks.
A single clock or dual clock FIFO may be
implemented in the M4K blocks. Simultaneous
read and write from an empty FIFO buffer is not
supported.
Description
Altera Corporation
February 2007

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