EP2C8T144I8N Altera, EP2C8T144I8N Datasheet - Page 41

IC CYCLONE II FPGA 8K 144-TQFP

EP2C8T144I8N

Manufacturer Part Number
EP2C8T144I8N
Description
IC CYCLONE II FPGA 8K 144-TQFP
Manufacturer
Altera
Series
Cyclone® IIr
Datasheet

Specifications of EP2C8T144I8N

Number Of Logic Elements/cells
8256
Number Of Labs/clbs
516
Total Ram Bits
165888
Number Of I /o
85
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
144-TQFP, 144-VQFP
Family Name
Cyclone® II
Number Of Logic Blocks/elements
8256
# I/os (max)
85
Frequency (max)
402.58MHz
Process Technology
90nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
8256
Ram Bits
165888
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
144
Package Type
TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2157

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Altera Corporation
February 2007
Note to
(1)
Maximum performance
Total RAM bits per M4K block (including parity bits)
Configurations supported
Parity bits
Byte enable
Packed mode
Address clock enable
Memory initialization file (.mif)
Power-up condition
Register clears
Same-port read-during-write
Mixed-port read-during-write
Table 2–6. M4K Memory Features
Maximum performance information is preliminary until device characterization.
Table
2–6:
Feature
(1)
Table 2–6
summarizes the features supported by the M4K memory.
250 MHz
4,608
2K × 2
1K × 4
512 × 8
512 × 9
256 × 16
256 × 18
128 × 32 (not available in true dual-port mode)
128 × 36 (not available in true dual-port mode)
One parity bit for each byte. The parity bit, along with
internal user logic, can implement parity checking for
error detection to ensure data integrity.
a data width of 1, 2, 4, 8, 9, 16, 18, 32, or 36 bits. The
byte enables allow the input data to be masked so the
device can write to specific bytes. The unwritten bytes
retain the previous written value.
Two single-port memory blocks can be packed into a
single M4K block if each of the two independent block
sizes are equal to or less than half of the M4K block
size, and each of the single-port memory blocks is
configured in single-clock mode.
used to hold the previous address value for as long as
the signal is enabled. This feature is useful in handling
misses in cache applications.
When configured as RAM or ROM, you can use an
initialization file to pre-load the memory contents.
Output registers only
New data available at positive clock edge
4K × 1
M4K blocks support byte writes when the write port has
M4K blocks support address clock enable, which is
Outputs cleared
Old data available at positive clock edge
Cyclone II Device Handbook, Volume 1
Description
Cyclone II Architecture
2–29

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