MT46H32M16LFCK-10 Micron Technology Inc, MT46H32M16LFCK-10 Datasheet - Page 6

• Manufacturer Part Number: MT46H32M16LFCK-10
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr

Specifications of MT46H32M16LFCK-10

• Organization: 32Mx16
• Density: 512Mb
• Address Bus: 15b
• Access Time (max): 7ns
• Maximum Clock Rate: 104MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 90mA
• Pin Count: 60
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

PDF: 09005aef818ff7c5/Source: 09005aef81a6c5f3
MT46H32M16LF_2..fm - Rev. F 09/05 EN
Notes: 1. Throughout the data sheet, the various figures and text refer to DQs as “DQ.” The DQ
2. Complete functionality is described throughout the document and any page or dia-
3. Any specific requirement takes precedence over a general statement.
with the ACTIVE command are used to select the bank and row to be accessed. The
address bits registered coincident with the READ or WRITE command are used to select
the bank and the starting column location for the burst access.
The Mobile DDR SDRAM provides for programmable READ or WRITE burst lengths of 2,
4, 8, 16 or continuous page. An AUTO-PRECHARGE function may be enabled to provide
a self-timed row precharge that is initiated at the end of the burst access.
As with standard SDR SDRAMs, the pipelined, multibank architecture of Mobile DDR
SDRAMs allows for concurrent operation, thereby providing high effective bandwidth by
hiding row precharge and activation time.
An auto-refresh mode is provided, along with a power saving power down mode. Deep
power-down mode is offered to achieve maximum power reduction by eliminating the
power of the memory array. Data will not be retained once the device enters deep power-
down mode.
Micron's 512Mb Mobile DDR SDRAM device features Endur-IC technology. Pairing
Micron's advanced memory architecture with innovative Endur-IC technology results in
Mobile DDR devices that exceed current JEDEC standards, including lower power speci-
fications that dramatically reduce overall power consumption.
Two self refresh features, temperature compensated self refresh (TCSR) and partial array
self refresh (PASR), offer additional power savings. TCSR is controlled by the automatic
on-chip temperature sensor. The PASR can be customized using the extended mode reg-
ister settings. The two features may be combined to achieve even greater power savings.
term is to be interpreted as any and all DQ collectively, unless specifically stated oth-
erwise. Additionally, the x16 is divided into two bytes—the lower byte and upper byte.
For the lower byte (DQ0–DQ7) DM refers to LDM and DQS refers to LDQS; and for the
upper byte (DQ8–DQ15) DM refers to UDM and DQS refers to UDQS. The x32 is
divided into four bytes. For DQ0–DQ7, DM refers to DM0 and DQS refers to DQS0; for
DQ8–DQ15, DM refers to DM1 and DQS refers to DQS1; for DQ16–DQ23, DM refers to
DM2 and DQS refers to DQS2; and for DQ24–DQ31, DM refers to DM3 and DQS refers
to DQS3.
gram may have been simplified to convey a topic and may not be inclusive of all
requirements.
6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512Mb: x16, x32 Mobile DDR SDRAM
General Description
©2005 Micron Technology, Inc. All rights reserved.
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