MT46H32M16LFCK-10 Micron Technology Inc, MT46H32M16LFCK-10 Datasheet - Page 27

• Manufacturer Part Number: MT46H32M16LFCK-10
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr

Specifications of MT46H32M16LFCK-10

• Organization: 32Mx16
• Density: 512Mb
• Address Bus: 15b
• Access Time (max): 7ns
• Maximum Clock Rate: 104MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 90mA
• Pin Count: 60
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

Figure 11:
READs
PDF: 09005aef818ff7c5/Source: 09005aef81a6c5f3
MT46H32M16LF_2..fm - Rev. F 09/05 EN
COMMAND
BA0, BA1
A0–A12
CK#
CK
Example: Meeting
Bank x
Row
ACT
T0
READ burst operations are initiated with a READ command, as shown in Figure 12 on
page 28.
The starting column and bank addresses are provided with the READ command and
auto precharge is either enabled or disabled for that burst access. If auto precharge is
enabled, the row being accessed is precharged at the completion of the burst. For the
READ commands used in the following illustrations, auto precharge is disabled.
During READ bursts, the valid data-out element from the starting column address will
be available following the CAS latency after the READ command. Each subsequent data-
out element will be valid nominally at the next positive or negative clock edge (i.e., at the
next crossing of CK and CK#). Figure 13 on page 29 shows general timing for each possi-
ble CAS latency setting. DQS is driven by the Mobile DDR SDRAM along with output
data. The initial LOW state on DQS is known as the read preamble; the LOW state coinci-
dent with the last data-out element is known as the read postamble.
Upon completion of a burst, assuming no other commands have been initiated, the DQs
will go High-Z. A detailed explanation of
window hold), the valid data window are depicted in Figure 31 on page 46. A detailed
explanation of
CK) is depicted in Figure 38 on page 69.
Data from any READ burst may be concatenated with or truncated with data from a sub-
sequent READ command. In either case, a continuous flow of data can be maintained.
The first data element from the new burst follows either the last element of a completed
burst or the last desired data element of a longer burst which is being truncated. The
new READ command should be issued x cycles after the first READ command, where x
equals the number of desired data element pairs (pairs are required by the 2n-prefetch
architecture). This is shown in Figure 14 on page 30.
A READ command can be initiated on any clock cycle following a previous READ com-
mand. Nonconsecutive read data is shown for illustration in Figure 15 on page 31. Full-
speed random read accesses within a page (or pages) can be performed as shown in
Figure 16 on page 32.
NOP
T1
t
RCD (
t
RRD
t
DQSCK (DQS transition skew to CK) and
t
NOP
RRD) MIN When 2 <
T2
Bank y
27
ACT
Row
T3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
512Mb: x16, x32 Mobile DDR SDRAM
RCD (
t
DQSQ (valid data-out skew),
NOP
T4
t
RRD) MIN/
t
RCD
NOP
t
T5
AC (data-out transition skew to
t
CK ≤ 3
©2005 Micron Technology, Inc. All rights reserved.
RD/WR
Bank y
Col
T6
t
QH (data-out
Operations
DON’T CARE
Advance
NOP
T7