ST7265XEVALMS STMicroelectronics, ST7265XEVALMS Datasheet - Page 93

• Manufacturer Part Number: ST7265XEVALMS
• Manufacturer: STMicroelectronics

Specifications of ST7265XEVALMS

• Lead Free Status / Rohs Status: Supplier Unconfirmed

PWM/BRM GENERATOR (Cont’d)
Figure 54. Precision for PWM/BRM Tuning for VOUTEFF (After filtering)
11.5.4 Register Description
On a channel basis, the 10 bits are separated into
two data registers:
Note: The number of PWM and BRM channels
available depends on the device. Refer to the de-
vice pin description and register map.
PULSE BINARY WEIGHT REGISTERS (PWMi)
Read / Write
Reset Value 1000 0000 (80h)
Bit 7 = Reserved (Forced by hardware to “1”)
Bit 6 = POL Polarity Bit for channel i.
0: The channel i outputs a “1” level during the bina-
1: The channel i outputs a “0” level during the bina-
Bit 5:0 = P[5:0] PWM Pulse Binary Weight for
channel i.
This register contains the binary value of the pulse.
For example
Effective (with external RC filtering) DAC value
ry pulse and a “0” level after.
ry pulse and a “1” level after.
7
1
1
1
POL
POL
POL
:
P5
P
P4
P
P3
P
P
P2
P
P
P1
P
P0
0
P
P
BRM REGISTERS
Read / Write
Reset Value: 0000 0000 (00h)
These registers define the intervals where an in-
cremental pulse is added to the beginning of the
original PWM pulse. Two BRM channel values
share the same register.
Bit 7:4 = B[7:4] BRM Bits (channel i+1).
Bit 3:0 = B[3:0] BRM Bits (channel i)
Note: From the programmer's point of view, the
PWM and BRM registers can be regarded as be-
ing combined to give one data value.
P
B7
7
P
B6
P
+
B5
B
B4
B
B3
B
B
B2
B
B
B1
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B
B0
B
0