ST7265XEVALMS STMicroelectronics, ST7265XEVALMS Datasheet - Page 161

• Manufacturer Part Number: ST7265XEVALMS
• Manufacturer: STMicroelectronics

Specifications of ST7265XEVALMS

• Lead Free Status / Rohs Status: Supplier Unconfirmed

16 IMPORTANT NOTES
16.1 SPI Multimaster Mode
Multi master mode is not supported.
16.2
previously
Watchdog option
Description
In-Circuit Programming of devices configured with
Hardware Watchdog (WDGSW bit in option byte 1
programmed to 0) requires certain precautions
(see below).
In-Circuit Programming uses ICC mode. In this
mode, the Hardware Watchdog is not automatical-
ly deactivated as one might expect. As a conse-
quence, internal resets are generated every 2 ms
by the watchdog, thus preventing programming.
The device factory configuration is Software
Watchdog so this issue is not seen with devices
that are programmed for the first time. For the
same reason, devices programmed by the user
with the Software Watchdog option are not impact-
ed.
The only devices impacted are those that have
previously been programmed with the Hardware
Watchdog option.
In-Circuit
programmed
Programming
with
of
Hardware
devices
Workaround
Devices configured with Hardware Watchdog
must be programmed using a specific program-
ming mode that ignores the option byte settings. In
this mode, an external clock, normally provided by
the programming tool, has to be used. In ST tools,
this mode is called "ICP OPTIONS DISABLED".
Sockets on ST programming tools (such as
ST7MDT10-EPB) are controlled using "ICP OP-
TIONS DISABLED" mode. Devices can therefore
be reprogrammed by plugging them in the ST Pro-
gramming Board socket, whatever the watchdog
configuration.
When using third-party tools, please refer the
manufacturer's documentation to check how to ac-
cess specific programming modes. If a tool does
not have a mode that ignores the option byte set-
tings, devices programmed with the Hardware
watchdog option cannot be reprogrammed using
this tool.
16.3 Unexpected Reset Fetch
Description
If an interrupt request occurs while a "POP CC" in-
struction is executed, the interrupt controller does
not recognise the source of the interrupt and, by
default, passes the RESET vector address to the
CPU.
Workaround
To solve this issue, a "POP CC" instruction must
always be preceded by a "SIM" instruction.
16.4 I2C Multimaster
In multimaster configurations, if the ST7 I2C re-
ceives a START condition from another I2C mas-
ter after the START bit is set in the I2CCR register
and before the START condition is generated by
the ST7 I2C, it may ignore the START condition
from the other I2C master. In this case, the ST7
master will receive a NACK from the other device.
On reception of the NACK, ST7 can send a re-start
and Slave address to re-initiate communication.
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