ST7265XEVALMS STMicroelectronics, ST7265XEVALMS Datasheet - Page 147

• Manufacturer Part Number: ST7265XEVALMS
• Manufacturer: STMicroelectronics

Specifications of ST7265XEVALMS

• Lead Free Status / Rohs Status: Supplier Unconfirmed

COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d)
13.11.3 I
1) The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge
2) The maximum hold time of the START condition has only to be met if the interface does not stretch the
Cb = total capacitance of one bus line in pF
Bus free time between a STOP and START con-
dition
Hold time START condition. After this period,
LOW period of the SCL clock
HIGH period of the SCL clock
Set-up time for a repeated START condition
Data hold time
Data set-up time
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Set-up time for STOP condition
Capacitive load for each bus line
the first clock pulse is generated
the undefined region of the falling edge of SCL
low period of SCL signal
2
C - Inter IC Control Interface
Parameter
I
2
C-Bus Timings
4.7
4.0
4.7
4.0
4.7
0 (1)
250
4.0
Min
Standard I
1000
300
400
Max
2
C
1.3
0.6
1.3
0.6
0.6
0 (1)
100
20+0.1Cb
20+0.1Cb
0.6
Min
Fast I
2
C
0.9(2)
300
300
400
Max
T
T
T
T
T
T
TF
T
T
T
Cb
Symbol
BUF
HD:STA
LOW
HIGH
SU:STA
HD:DAT
SU:DAT
R
SU
:
STO
ST7265x
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ms
µs
µs
µs
µs
ns
ns
ns
ns
ns
pF
Unit