ST7265XEVALMS STMicroelectronics, ST7265XEVALMS Datasheet - Page 44

• Manufacturer Part Number: ST7265XEVALMS
• Manufacturer: STMicroelectronics

Specifications of ST7265XEVALMS

• Lead Free Status / Rohs Status: Supplier Unconfirmed

ST7265x
8 POWER SAVING MODES
8.1 INTRODUCTION
To give a large measure of flexibility to the applica-
tion in terms of power consumption, two main pow-
er saving modes are implemented in the ST7.
After a RESET the normal operating mode is se-
lected by default (RUN mode). This mode drives
the device (CPU and embedded peripherals) by
means of a master clock which is based on the
main oscillator frequency divided by 2 (f
From Run mode, the different power saving
modes may be selected by setting the relevant
register bits or by calling the specific ST7 software
instruction whose action depends on the oscillator
status.
The user can also switch off any unused on-chip
peripherals individually by programming the
MISCR2 register.
8.2 WAIT MODE
WAIT mode places the MCU in a low power con-
sumption mode by stopping the CPU.
This power saving mode is selected by calling the
“WFI” ST7 software instruction.
All peripherals remain active. During WAIT mode,
the
enable all interrupts. All other registers and mem-
ory remain unchanged. The MCU remains in WAIT
mode until an interrupt or Reset occurs, whereup-
on the Program Counter branches to the starting
address of the interrupt or Reset service routine.
The MCU will remain in WAIT mode until a Reset
or an Interrupt occurs, causing it to wake up.
Refer to
44/163
1
I1:0] bits
Figure
in the CC register are forced to 0, to
29.
CPU
).
Figure 29. WAIT Mode Flow Chart
Note: Before servicing an interrupt, the CC
register is pushed on the stack. The
set during the interrupt routine and cleared
when the CC register is popped.
N
INTERRUPT
Y
OSCILLATOR
PERIPH. CLOCK
CPU CLOCK
I1:0] BITS
N
OR SERVICE INTERRUPT
OSCILLATOR
PERIPH. CLOCK
CPU CLOCK
FETCH RESET VECTOR
I1:0] BITS
WFI INSTRUCTION
(Refer to
Figure
IF RESET
DELAY
RESET
Figure 19
20)
Y
ON
ON
OFF
CLEARED
I1:0] bits
and
ON
ON
ON
SET
are