ST7265XEVALMS STMicroelectronics, ST7265XEVALMS Datasheet - Page 63

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ST7265XEVALMS

Manufacturer Part Number
ST7265XEVALMS
Description
Manufacturer
STMicroelectronics
Datasheet

Specifications of ST7265XEVALMS

Lead Free Status / Rohs Status
Supplier Unconfirmed
USB INTERFACE (Cont’d)
USB Endpoint RAM Buffers
There are five bidirectional Endpoints including
one control Endpoint 0. Endpoint 1 and Endpoint 2
are counted as 4 bulk or interrupt Endpoints (two
IN and two OUT).
Endpoint 0 and Endpoint 1 are both 2 x 16 bytes in
size. Endpoint 2 is 2 x 64 bytes in size and can be
configured to physically target different USB Data
Buffer areas depending on the MOD[1:0] bits in
Figure 37. Endpoint 2 Normal Mode selected by (MOD[1:0] Bits = 00h)
Figure 38. Endpoint 2 Download Mode selected by MOD[1:0] Bits = 10b
1550h
158Fh
Endpoint 2 Buffer OUT
Endpoint 0 Buffer OUT
Endpoint 1 Buffer OUT
Endpoint 2 Buffer IN
Endpoint 0 Buffer IN
Endpoint 1 Buffer IN
1550h
155Fh
156Fh
157Fh
158Fh
15CFh
160Fh
Endpoint 2 Buffer IN
Endpoint 2 Buffer OUT
Endpoint 0 Buffer OUT
Endpoint 1 Buffer OUT
Endpoint 0 Buffer IN
Endpoint 1 Buffer IN
the CTLR register (see
Figure
The USB Data Buffer operates as a double buffer;
while one 512-byte block is being read/written by
the DTC, the USB interface reads/writes the other
512-byte block.
The management of the data transfer is performed
in upload and download mode (2 x 512 byte buff-
ers for Endpoint 2) by the USB Data Buffer Manag-
er.
15CFh
1A4Fh
1590h
1650h
39).
16 Bytes
16 Bytes
16 Bytes
16 Bytes
64 Bytes
64 Bytes
USB DATA
USB DATA
USB DATA
USB DATA
USB DATA
Figure
64-byte buffer
512-byte buffer
as 64-byte slices
512-byte buffer
as 64-byte slices
37,
Figure 38
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