ST7265XEVALMS STMicroelectronics, ST7265XEVALMS Datasheet - Page 110

• Manufacturer Part Number: ST7265XEVALMS
• Manufacturer: STMicroelectronics

Specifications of ST7265XEVALMS

• Lead Free Status / Rohs Status: Supplier Unconfirmed

ST7265x
I²C SINGLE MASTER BUS INTERFACE (Cont’d)
11.7.5 Low Power Modes
11.7.6 Interrupts
Figure 65. Event Flags and Interrupt Generation
Note: The I
the same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding
Enable Control Bit is set and the I-bits in the CC
register are reset (RIM instruction).
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WAIT
HALT
End of Byte Transfer Event
Start Bit Generation Event (Master mode)
Acknowledge Failure Event
Mode
*
EVF can also be set by EV2 or an error from the SR2 register.
BTF
*
SB
No effect on I
I
I
In HALT mode, the I
resumes operation when the MCU is woken up by an interrupt with “exit from HALT mode” capability.
AF
2
2
2
C interrupts cause the device to exit from WAIT mode.
C registers are frozen.
*
C interrupt events are connected to
2
C interface.
Interrupt Event
2
C interface is inactive and does not acknowledge data on the bus. The I
ITE
Description
Event
Flag
BTF
SB
AF
Control
Enable
Bit
ITE
INTERRUPT
EVF
from
Wait
Exit
Yes
Yes
Yes
2
C interface
from
Halt
Exit
No
No
No