JG82855GME S L7VN Intel, JG82855GME S L7VN Datasheet - Page 92

• Manufacturer Part Number: JG82855GME S L7VN
• Manufacturer: Intel

Specifications of JG82855GME S L7VN

• Package Type: FCBGA
• Rad Hardened: No
• Lead Free Status / Rohs Status: Compliant

92
Register Description
4.9.11
4.9.12
CAPPTR – Capabilities Pointer Register
Address Offset:
Default Value:
Access:
Size:
The CAPPTR provides the offset that is the pointer to the location of the first device capability in
the capability list.
DRB – DRAM Row (0:3) Boundary Register (Device #0)
Address Offset:
Default Value:
Access:
Size:
The DDR SDRAM Row Boundary Register defines the upper boundary address of each DDR
SDRAM row with a granularity of 32-MB. Each row has its own single-byte DRB register. For
example, a value of 1 in DRB0 indicates that 32-MB of DDR SDRAM has been populated in the
first row. Since the GMCH supports a total of four rows of system memory, DRB0-3 are used.
The registers from 44h-4Fh are Reserved for DRBs 4-15.
Row0: 40h
Row1: 41h
Row2: 42h
Row3: 43h
44h to 4Fh is reserved.
DRB0 = Total system memory in Row0 (in 32 -MB increments)
DRB1 = Total system memory in Row0 + Row1 (in 32 -MB increments)
DRB2 = Total system memory in Row0 + Row1 + Row2 (in 32 -MB increments)
DRB3 = Total system memory in Row0 + Row1 + Row2 + Row3 (in 32- MB increments)
7:0
7:0
Each Row is represented by a Byte. Each Byte has the following format.
Bit
Bit
DDR SDRAM Row Boundary Address: This 8-bit value defines the upper and lower addresses for each
DDR SDRAM row. This 8-bit value is compared against a set of address lines to determine the upper
address limit of a particular row. Also the minimum system memory supported is 64-MB in 64-Mb
granularity; hence bit 0 of this register must be programmed to a zero.
Pointer to the offset of the first capability ID register block: In this case there are no capabilities,
therefore these bits are hardwired to 00h to indicate the end of the capability linked list.
34h
00h
Read Only
8 bits
40-43h
00h each
Read/Write
8 bits each
Description
Description
Datasheet
R