JG82855GME S L7VN Intel, JG82855GME S L7VN Datasheet - Page 115

• Manufacturer Part Number: JG82855GME S L7VN
• Manufacturer: Intel

Specifications of JG82855GME S L7VN

• Package Type: FCBGA
• Rad Hardened: No
• Lead Free Status / Rohs Status: Compliant

Datasheet
4.11.4
R
PCISTS – PCI Status Register (Device #2)
Address Offset:
Default Value:
Access:
Size:
PCISTS is a 16-bit status register that reports the occurrence of a PCI compliant master abort and
PCI compliant target abort. PCISTS also indicates the DEVSEL# timing that has been set by the
IGD.
2
1
0
15
14
13
12
11
10:9
8
7
6
5
4
3:0
Bit
Bit
Detected Parity Error (DPE): Since the IGD does not detect parity, this bit is always set to 0.
Signaled System Error (SSE) – RO
Received Master Abort Status (RMAS) – RO
Received Target Abort Status (RTAS) – RO
Signaled Target Abort Status (STAS) – RO
DEVSEL# Timing (DEVT) – RO
Data Parity Detected (DPD) – RO
Fast Back-to-Back (FB2B) – RO
User Defined Format (UDF) – RO
66 MHz PCI Capable (66C) – RO
CAP LIST: This bit is set to 1 to indicate that the register at 34h provides an offset into the Function’s PCI
Configuration Space containing a pointer to the location of the first item in the list.
Reserved
Bus Master Enable (BME) ⎯R/W: This bit determines if the IGD is to function as a PCI compliant
master.
0= Disable IGD bus mastering (default).
1 = Enable IGD bus mastering.
Memory Access Enable (MAE) ⎯R/W: This bit controls the IGD’s response to System Memory Space
accesses.
0= Disable (default).
1 = Enable.
I/O Access Enable (IOAE) ⎯R/W: This bit controls the IGD’s response to I/O Space accesses.
0 = Disable (default).
1 = Enable.
06−07h
0090h
Read Only
16 bits
Description
Description
Register Description
115