JG82855GME S L7VN Intel, JG82855GME S L7VN Datasheet - Page 29

• Manufacturer Part Number: JG82855GME S L7VN
• Manufacturer: Intel

Specifications of JG82855GME S L7VN

• Package Type: FCBGA
• Rad Hardened: No
• Lead Free Status / Rohs Status: Compliant

Datasheet
3
R
Signal Descriptions
This section describes the GMCH signals. These signals are arranged in functional groups
according to their associated interface. The following notations are used to describe the signal
type:
I
O
I/O
The signal description also includes the type of buffer used for the particular signal:
AGTL+
DVO
Hub
SSTL_2
LVTTL
CMOS
LVDS
Analog
Ref
System Address and Data Bus signals are logically inverted signals. In other words, the actual
values are inverted of what appears on the system bus. This must be taken into account and the
addresses and data bus signals must be inverted inside the GMCH. All processor control signals
follow normal convention: A 0 indicates an active level (low voltage), and a 1 indicates an active
level (high voltage).
Input pin
Output pin
Bi-directional Input/Output pin
Open Drain AGTL+ interface signal. Refer to the AGTL+ I/O Specification for
complete details. The GMCH integrates AGTL+ termination resistors, and supports
VTTLF of 1.05 V ± 5%. AGTL+ signals are “inverted bus” style where a low
voltage represents a logical 1.
DVO buffers (1.5 V tolerant)
Compatible to Hub interface 1.5
Low Voltage TTL compatible signals (3.3 V tolerant)
CMOS buffers (3.3 V tolerant)
Low Voltage Differential signal interface
Analog signal interface
Voltage reference signal
Stub Series Termination Logic compatible signals (2.5 V tolerant)
Signal Descriptions
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