JG82855GME S L7VN Intel, JG82855GME S L7VN Datasheet - Page 186

• Manufacturer Part Number: JG82855GME S L7VN
• Manufacturer: Intel

Specifications of JG82855GME S L7VN

• Package Type: FCBGA
• Rad Hardened: No
• Lead Free Status / Rohs Status: Compliant

186
Video Filter Capacitors and Ferrite Bead Arranged in a
PI Configuration (One PI Filter Testability)
9.1
Figure 11. XOR Chain Test Mode Entry Events Diagram
Figure 12. ALLZ Test Mode Entry Events Diagram
XOR Test Mode Entry
NOTE: HSYNC and LCLKCTLA = XOR Chain Test Mode Activation; No clock is required for XOR Chain Test
NOTE: VSYNC and LCLKCTLA = ALL Z Test Mode Activation; No clock is required for ALLZ Test Mode
Mode. A minimum of 50 ns PWROK assertion prior to RSTIN# assertion is recommended. A minimum
of 10 ns VSYNC/HSYNC/LCLKCTLA assertion prior to PWROK assertion is recommended.
Activation. A minimum of 50 ns PWROK assertion prior to RSTIN# assertion is recommended. A
minimum of 10 ns VSYNC/HSYNC/LCLKCTLA assertion prior to PWROK assertion is recommended.
L C L K C T L A
R S T I N #
R S T I N #
L C L K C T L A
p o w e r o k
V S Y N C
H S Y N C
p o w e r o k
V S Y N C
H S Y N C
( P C I r e s e t )
( P C I r e s e t )
D o n ' t c a r e
D o n ' t c a r e
D o n 't c a r e
D o n 't c a r e
D o n 't c a r e
D o n 't c a r e
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