JG82855GME S L7VN Intel, JG82855GME S L7VN Datasheet
JG82855GME S L7VN
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... R ® Intel 855GM/855GME Chipset Graphics and Memory Controller Hub (GMCH) Datasheet April 2005 Document Number: 252615-005 ...
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... C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips Corporation. Intel, Pentium, Celeron, Intel SpeedStep, and Intel Centrino and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. ...
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... AGP Flow Control Signals .................................................................... 35 AGP Status Signals .............................................................................. 35 AGP Strobes ......................................................................................... 36 AGP/PCI Signals-Semantics ................................................................ 36 Dedicated LVDS LCD Flat Panel Interface........................................... 41 Digital Video Output B (DVOB) Port ..................................................... 42 ® 2 Intel 855GME GMCH DVO AGP Pin Mapping ......................... 42 Digital Video Output C (DVOC) Port..................................................... 44 Analog CRT Display ............................................................................. 45 General Purpose Input/Output Signals................................................. 46 3 ...
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... Intel 855GM/GME GMCH Main Memory Control, Memory I/O Control Registers (Device #0, Function #1) ...................................................................................... 86 4.9.1 4 PCI Bus #0 Configuration Mechanism.................................................. 53 Primary PCI and Downstream Configuration Mechanism .................... 54 AGP/PCI_B Bus Configuration Mechanism.......................................... 54 CONFIG_ADDRESS – Configuration Address Register ...................... 56 CONFIG_DATA – ...
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... ID – Subsystem Identification Register............................................... 109 4.10.11 CAPPTR – Capabilities Pointer Register............................................ 110 4.10.12 HPLLCC – HPLL Clock Control Register (Device #0)........................ 110 ® 4.11 Intel 852GM GMCH Integrated Graphics Device Registers (Device #2, Function #0)........................................................................................................ 113 4.11.1 4.11.2 4.11.3 4.11.4 4.11.5 4 ...
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... DDR SDRAM Performance Description ............................................. 140 6.3.3.1 Data Integrity (ECC) .......................................................... 140 3D/2D Instruction Processing ............................................................. 141 3D Engine ........................................................................................... 141 6.4.2.1 Bi-Cubic Filtering (Intel 6.4.2.2 Video Mixer Rendering (Intel 6.4.2.3 Setup Engine ..................................................................... 142 6.4.2.4 Viewport Transform and Perspective Divide ..................... 142 6.4.2.5 3D Primitives and Data Formats Support.......................... 143 6.4.2.6 Pixel Accurate Fast Scissoring and Clipping Operation ...
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R 6.4.3 6.4.4 6.4.5 6.4.6 6.4.7 6.4.8 6.5 Display Interface................................................................................................. 153 6.5.1 6.5.2 Datasheet 6.4.2.8 Scan Converter.................................................................. 143 6.4.2.9 Texture Engine .................................................................. 143 6.4.2.10 Perspective Correct Texture Support................................ 144 6.4.2.11 Texture Decompression .................................................... 144 6.4.2.12 Texture Chromakey........................................................... 144 6.4.2.13 Anti-Aliasing....................................................................... ...
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... Panel Power Sequence States.......................... 156 6.5.2.8 Back Light Inverter Control................................................ 157 6.5.2.9 Digital Video Output Port................................................... 157 6.5.2.10 Intel 855GME GMCH AGP Interface Overview................. 158 6.5.2.11 AGP Target Operations..................................................... 158 AGP Transaction Ordering ................................................................. 159 AGP Signal Levels .............................................................................. 159 4X AGP Protocol................................................................................. 159 6 ...
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... GMCH Micro-FCBGA Package Dimensions (Top View)................................................................................................................ 211 ® Figure 15. Intel 855GM/855GME GMCH Micro-FCBGA Package Dimensions (Side View)............................................................................................................... 212 ® Figure 16. Intel 855GM/855GME GMCH Micro-FCBGA Package Dimensions (Bottom View) .......................................................................................................... 213 Tables Table 1. DDR SDRAM Memory Capacity ......................................................................... 25 ® Table 2. Intel 855GM/855GME GMCH Interface Clocks ................................................ 28 Table 3 ...
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... Table 35. Relation of DBI Bits to Data Bits ..................................................................... 137 Table 36. Data Bytes on SO-DIMM Used for Programming DRAM Registers............... 139 Table 37. Dual Display Usage Model (Intel Table 38. Panel Power Sequencing Timing Parameters................................................ 157 Table 39. AGP Commands Supported by the GMCH when Acting as an AGP Target . 158 Table 40 ...
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... Changed naming convention for Host Bus from Processor System Bus (PSB) to Front Side Bus (FSB) • Added 855GME features and system diagram to features section • Section 1: Added disclaimer for Intel • Updated Reference Documents list • Section 2: Added System architecture details for 855GM/855GME • ...
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... Revision Number 005 Updates include: • Added new Chapter 8 Electrical Characteristics • Testability moved to Chapter 9 • Intel 855GM/GME GMCH Strap Pins is now Chapter 10 Ballout and Package Information is now Chapter 11 12 Description ⎯ Absolute Maximum Ratings ⎯ Thermal Characteristics ⎯ Power Characteristics ⎯ ...
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... Page size is individually selected for every row ⎯ UMA support only System Interrupts ⎯ Supports Intel 8259 and front side bus interrupt delivery mechanism ⎯ Supports interrupts signaled as upstream memory writes from PCI and Hub interface ⎯ MSI sent to the CPU through the system bus ⎯ ...
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DVO (DVOB and DVOC) support • Digital video out ports DVOB and DVOC with 165 MHz dot clock on each 12-bit interface; two 12-bit channels can be combined to form one dual channel 24-bit interface with an effective dot ...
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R • Twelve level of detail MIP map sizes from 1x1 • Numerous texture formats including 32- bit RGBA • Alpha and Luminance maps • Texture chromakeying • Bilinear, trilinear, and anisotropic MIP map filtering • ...
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... Figure 1. Intel 855GM GMCH Chipset System Block Diagram CK-408 DVI DVOB & DVOC Device 1.5 V CRT LVDS Hub Interface 1.5 ATA100 IDE (2) USB2.0/1.1 (6) LAN AC'97 2.2/2.3 Modem Codec Audio Codec 16 Intel® Pentium® M Processor OR IMVP-IV Intel® Celeron® M ...
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... R ® Intel 855GME Chipset GMCH Features Note: The Intel 855GME chipset GMCH has identical features to the Intel 855GM chipset GMCH except for the additional features listed below. Processor/Host Bus Support ⎯ Pin and spec compatible with the Intel ® Pentium M processor, Intel ...
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... Figure 2. Intel 855GME GMCH Chipset System Block Diagram CK-408 DVI/AGP DVOB/C or AGP Device LVDS ATA100 IDE (2) USB2.0/1.1 (6) LAN Modem Codec 18 Intel® Pentium® M Processor OR Intel® Celeron® M Processor 400 MHz FSB 1.5 V Intel® 855GME GMCH CRT 732 Micro- FCBGA Hub Interface 1 ...
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... This datasheet provides Intel’s specifications for the Intel system. The Intel 855GM/855GME chipset graphics and memory controller hub (GMCH) is also an Intel Centrino™ mobile technology component. Intel Centrino mobile technology with integrated wireless LAN capabilities was designed specifically for wireless notebook PCs – delivering outstanding mobile performance and enabling extended battery life, and thinner, lighter designs ...
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... Scalable bus is the P6 Bus plus enhancements, consisting of source synchronous transfers for address and data, and system bus interrupt delivery. The Intel Pentium M processor, Intel Pentium M on 90nm process with 2-MB L2 Cache and Intel Celeron M processor implement a subset of Enhanced mode. Unified Memory Architecture with graphics memory for the IGD inside system ...
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... Management(ACPI) Specification 1.0b & 2.0 Advanced Power Management (APM) Specification 1.2 ® IA-32 Intel Architecture Software Developer Manual Volume 3: System Programming Guide (253668) NOTES: 1. Contact your Intel representative for the current document. Datasheet Location http://www.intel.com/design/mobile/datashts/252612.h tm http://developer.intel.com/design/mobile/datashts/302 189.htm http://www.intel.com/design/mobile/datashts/300302.h ...
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Introduction 22 R Datasheet ...
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... Intel 855GME Chipset GMCH The Intel 855GME GMCH 732-pin Micro-FCBGA package and contains all features listed above and the additional functionality list below: • Display Core frequency at 133 MHz, 200 MHz, or 250 MHz • Render Core frequency at 100 MHz ,133 MHz, 166 MHz, 200 MHz, or 250 MHz • ...
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... Intel® 855GM/855GME Chipset GMCH Overview 2.2 Processor Host Interface The Intel 855GM/855GME GMCH is optimized for the Intel Pentium M processor and Intel Celeron M processor Key features of the front side bus (FSB) are: • Support for a 400 MHz system bus frequency. • Source synchronous double pumped address (2X) • ...
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... High bandwidth access to data is provided through the system memory interface. The GMCH uses Tiling architecture to increase system memory efficiency and thus maximize effective rendering bandwidth. The Intel 855GM/855GME GMCH improves 3D performance and quality with 3D Zone rendering technology. The Intel 855GME GMCH also supports Video Mixer rendering, and Bi-Cubic filtering. Datasheet Intel® ...
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... Intel 855GME GMCH AGP Interface The Intel 855GME has support for a single AGP component is supported by the AGP interface. The AGP buffers operate only in 1.5 V mode. They are not 3.3 V tolerant. The AGP interface supports 1X/2X/4X AGP signaling and 2X/4X Fast Writes. AGP semantic cycles to DDR SDRAM are not snooped on the host bus ...
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... MHz. The GMCH does not require any relationship between the BCLK Host clock and the 66 MHz clock generated for Hub interface; they are asynchronous to each other. The Hub interface runs at a constant 66 MHz base frequency. Table 2 indicates the frequency ratios between the various interfaces that the GMCH supports. Datasheet Intel® 855GM/855GME Chipset GMCH Overview 27 ...
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... Intel Pentium M processor and Intel Celeron M processor FSB interrupt delivery mechanism. The serial APIC Interrupt mechanism is not supported. The Intel 8259 Interrupt delivery mechanism support consists of flushing in bound Hub interface write buffers when an Interrupt Acknowledge cycle is forwarded from the system bus to the Hub interface ...
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R 3 Signal Descriptions This section describes the GMCH signals. These signals are arranged in functional groups according to their associated interface. The following notations are used to describe the signal type: I Input pin O Output pin I/O Bi-directional ...
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Signal Descriptions 3.1 Host Interface Signals Table 3. Host Interface Signal Descriptions Signal Name Type ADS# I/O Address Strobe: The system bus owner asserts ADS# to indicate the first of two AGTL+ cycles of a request phase. The GMCH can ...
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R Signal Name Type DRDY# I/O Data Ready: Asserted for each cycle that data is transferred. AGTL+ HA[31:3]# I/O Host Address Bus: HA[31:3]# connects to the CPU address bus. During processor AGTL+ cycles the HA[31:3]# are inputs. The GMCH drives ...
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Signal Descriptions Signal Name Type RS[2:0]# O Response Status: Indicates the type of response according to the following the table: AGTL+ 3.2 DDR SDRAM Interface Table 4. DDR SDRAM Interface Descriptions Signal Name Type SCS[3:0]# O Chip Select: These pins ...
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R Signal Name Type SDQS[8:0] I/O Data Strobes: Data strobes are used for capturing data. During writes, SDQS is SSTL_2 centered on data. During reads, SDQS is edge aligned with data. The following list matches the data strobe with the ...
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... Signal Descriptions 3.3 AGP Interface Signals Note: AGP interface is only supported on the Intel 855GME GMCH. Unless otherwise specified, the voltage level for all signals in this interface is 1.5 volts. 3.3.1 AGP Addressing Signals Table 5. AGP Addressing Signal Descriptions Signal Name Type GPIPE# ...
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R 3.3.2 AGP Flow Control Signals Table 6. AGP Flow Control Signals Signal Name Type GRBF# I Read Buffer Full: Read buffer full indicates if the master is ready to accept previously AGP requested low priority read data. When RBF# ...
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Signal Descriptions 3.3.4 AGP Strobes Table 8. AGP Strobe Descriptions Signal Name Type GADSTB[0] I/O Address/Data Bus Strobe-0: provides timing for 2X and 4X data on AD[15:0] and AGP C/BE[1:0]# signals. The agent that is providing the data will drive ...
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R Signal Name Type GIRDY# I/O G_IRDY#: Initiator Ready. AGP During PIPE# and SBA Operation: Not used while enqueueing requests via AGP SBA and PIPE#, but used during the data phase of PIPE# and SBA transactions. During FRAME# Operation: G_IRDY# ...
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Signal Descriptions Signal Name Type GGNT# O G_GNT#: Grant. AGP During SBA, PIPE# and FRAME# Operation: G_GNT#, along with the information on the ST[2:0] signals (status bus), indicates how the AGP interface will be used next. Refer to the AGP ...
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R 3.4 Hub Interface Signals Table 10. Hub Interface Signals Signal Name Type HL[10:0] I/O Packet Data: Data signals used for HI read and write operations. Hub HLSTB I/O Packet Strobe: One of two differential strobe signals used to transmit ...
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Signal Descriptions Signal Name Type DVOCCLK O DVOCCLK# DVO DVOBCCLKINT I DVO DPMS I DVO DAC Clocking DREFCLK I LVTTL LVDS LCD Flat Panel Clocking DREFSSCLK I LVTTL 40 Description Differential DVO Clock Output: These pins provide a differential pair ...
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R 3.6 Internal Graphics Display Signals The IGD has support for a dedicated LVDS LCD Flat Panel Interface, DVOB/C interfaces, and an Analog CRT port. 3.6.1 Dedicated LVDS LCD Flat Panel Interface Table 12. Dedicated LVDS LCD Flat Panel Interface ...
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... DVOBFLDSTL needs to be pulled down if not used. ® 3.6.3 Intel 855GME GMCH DVO/I The GMCH will mux a DVODETECT signal with the GPAR signal on the AGP bus. This signal will act as a strap and indicate whether the interface is in AGP or DVO mode. The GMCH has an internal 8 ...
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... R ® Table 14. Intel 855GME GMCH AGP/DVO Pin Muxing DVO MODE AGP MODE DVOBD[0] DVOBD[1] DVOBD[2] DVOBD[3] DVOBD[4] DVOBD[5] DVOBD[6] DVOBD[7] GCBE#[0] DVOBD[8] GAD[10] DVOBD[9] DVOBD[10] GAD[12] DVOBD[11] GAD[11] DVOBCLK GADSTB[0] DVOBCLK# GADSTB#[0] DVOBHSYNC DVOBVSYNC DVOBBLANK# GCBE#[1] DVOBFLDSTL GAD[14] Datasheet DVO MODE ...
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Signal Descriptions 3.6.4 Digital Video Output C (DVOC) Port Table 15. Digital Video Output C (DVOC) Port Signal Descriptions Name Type DVOCD[11:0] O DVOC Data: This data bus is used to drive 12-bit RGB data on each edge of the ...
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R 3.6.5 Analog CRT Display Table 17. Analog CRT Display Signal Descriptions Pin Name Type VSYNC O CRT Vertical Synchronization: This signal is used as the vertical sync signal. CMOS HSYNC O CRT Horizontal Synchronization: This signal is used as ...
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Signal Descriptions 3.6.6 General Purpose Input/Output Signals Table 18. GPIO Signal Descriptions GPIO I/F Total Type RSTIN# I Reset: Primary Reset, Connected to PCIRST# of ICH4-M. CMOS PWROK I Power OK: Indicates that power to GMCH is stable. CMOS AGPBUSY# ...
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R GPIO I/F Total Type MDVICLK I/O DVI DDC Clock: This signal is used as the DDC clock for a digital display connector (i.e. primary digital monitor). This signal is tri-stated during a hard reset. DVO MDVIDATA I/O DVI DDC ...
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Signal Descriptions 3.7 Voltage References, PLL Power Table 19. Voltage References, PLL Power Signal Name Type Host Processor HXRCOMP Analog Host RCOMP: Used to calibrate the Host AGTL+ I/O buffers. HYRCOMP Analog Host RCOMP: Used to calibrate the Host AGTL+ ...
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R Signal Name Type PSWING Analog RCOMP reference voltage: This is connected to the RCOMP buffer differential amplifier and is used to calibrate the buffers. HLVREF Ref Input buffer VREF: Input buffer differential amplifier to determine a high versus low ...
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Signal Descriptions 50 R Datasheet ...
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... Bus number. Note that the primary PCI bus is referred to as PCI_A in this document and is not PCI bus #0 from a configuration standpoint. For the Intel 855GME GMCH, the AGP appears to system software to be real PCI bus behind PCI-to-PCI bridges resident as devices on PCI bus #0. ...
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... In certain cases, Writes to “Reserved” registers may have no effect on the GMCH or may cause system failure. Registers that are marked as “Intel Reserved” must not be modified by system software. Upon Reset, the GMCH sets all of its internal configuration registers to predetermined default states ...
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R 4.3 Standard PCI Bus Configuration Mechanism The PCI Bus defines a slot based “configuration space” that allows each device to contain up to eight functions with each function containing up to 256, 8-bit configuration registers. The PCI Specification defines ...
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Register Description 4.4.2 Primary PCI and Downstream Configuration Mechanism If the Bus Number in the CONFIG_ADDRESS is non-zero, and is less than the value in the Host- AGP/PCI_B device’s Secondary bus number register or greater than the value in the ...
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R 4.5 Register Definitions The GMCH contains four sets of software accessible registers accessed via the Host CPU I/O Address Space, and they are as follows: • Control registers: I/O Mapped into the CPU I/O Space, which control access to ...
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Register Description 4.6 I/O Mapped Registers The GMCH contains two registers that reside in the CPU I/O Address Space: the Configuration Address (CONFIG_ADDRESS) Register and the Configuration Data (CONFIG_DATA) Register. The Configuration Address Register enables/disables the Configuration Space and determines ...
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R Bit 31 Configuration Enable (CFGE): When this bit is set to 1, accesses to PCI Configuration Space are enabled. If this bit is Reset to 0, accesses to PCI Configuration Space are disabled. 30:24 Reserved 23:16 Bus Number: When ...
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Register Description Bit 31:0 Configuration Data Window (CDW). If bit 31 of CONFIG_ADDRESS is 1, then any I/O access to the CONFIG_DATA register will be mapped to Configuration Space using the contents of CONFIG_ADDRESS. 4.7 VGA I/O Mapped Registers If ...
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... R ® 4.8 Intel 855GM/GME GMCH Host-Hub Interface Bridge Device Registers (Device #0, Function #0) Table 24 summarizes the configuration space for Device #0, Function#0. Table 24. GMCH Configuration Space - Device #0, Function#0 Register Name Vendor Identification Device Identification PCI Command PCI Status Revision Identification Sub-Class Code Base Class Code ...
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... The VID Register contains the vendor identification number. This 16-bit register, combined with the Device Identification Register, uniquely identifies any PCI device. Writes to this register have no effect. Bit 15:0 Vendor Identification (VID): This register field contains the PCI standard identification for Intel. 4.8.2 DID – Device Identification Register Address Offset: Default Value: ...
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R 4.8.3 PCICMD – PCI Command Register Address Offset: Default Value: Access: Size: Since GMCH Device #0 does not physically reside on PCI_A many of the bits are not implemented. Bit Descriptions 15:10 Reserved 9 Fast Back-to-Back Enable (FB2B): This ...
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Register Description 4.8.4 PCI Status Register Address Offset: Default Value: Access: Size: PCISTS is a 16-bit status register that reports the occurrence of error events on Device #0’s PCI Interface. Bit 14 is Read/Write Clear. All other bits are Read ...
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R 4.8.5 RID – Register Identification Address Offset: Default Value: Access: Size: This register contains the revision number of the GMCH Device #0. These bits are read only and writes to this register have no effect. Bit 7:0 Revision Identification ...
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Register Description 4.8.8 HDR – Header Type Register Address Offset: Default Value: Access: Size: This register identifies the header layout of the configuration space. No physical register exists at this location. Bit 7:0 PCI Header (HDR): This field always returns ...
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... This register is Read Only. Writes to this register have no effect. Bit 39:37 Capability ID [2:0]: 000 = Intel 855GME GMCH 001-011 = Reserved 100 = Intel 855GM GMCH 101-111 = Reserved 36:28 Reserved 27:24 CAPREG Version: This field has the value 0001b to identify the first revision of the CAPREG definition. ...
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Register Description 4.8.13 GMC – GMCH Miscellaneous Control Register (Device #0) Address Offset: Default Value: Access: Size: Bit 15:10 Reserved 9 Reserved 8 RRBAR Access Enable—R/ Enables the RRBAR space Disable 7:1 Reserved 0 MDA Present ...
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R 4.8.14 GGC – GMCH Graphics Control Register (Device 0) Address Offset: Default Value: Access: Size: Bit 15:7 Reserved 6:4 Graphics Mode Select (GMS): This field is used to select the amount of Main system memory that is pre-allocated to ...
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Register Description 4.8.15 DAFC – Device and Function Control Register (Device 0) Address Offset: Default Value: Access: Size: This 16-bit register controls the visibility of devices and functions within the GMCH to configuration software. Bit 15:8 Reserved 7 Device #2 ...
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R 4.8.17 PAM(6:0) – Programmable Attribute Map Register (Device #0) Address Offset: Default Value: Attribute: Size: The GMCH allows programmable DDR SDRAM attributes on 13 Legacy system memory segments of various sizes in the 640 kB –1 MB address range. ...
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Register Description Bits [7, 3] Bits [6, 2] Reserved Reserved example, consider a BIOS that is implemented on the Expansion bus. During the initialization process, the BIOS can be shadowed in main system memory to increase the ...
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R Table 26. PAM Registers and Associated System Memory Segments PAM Reg PAM0[3:0] PAM0[7:4] PAM1[3:0] PAM1[7:4] PAM2[3:0] PAM2[7:4] PAM3[3:0] PAM3[7:4] PAM4[3:0] PAM4[7:4] PAM5[3:0] PAM5[7:4] PAM6[3:0] PAM6[7:4] For details on overall system address mapping scheme see the Address Decoding section of ...
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Register Description Extended System BIOS Area (E0000h–EFFFFh) This 64-kB area is divided into four 16-kB segments that can be assigned with different attributes via PAM Control register as defined in Figure 5 and Table 26. System BIOS Area (F0000h–FFFFFh) This ...
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R 4.8.19 ESMRAMC – Extended System Management RAM Control (Device #0) Address Offset: Default Value: Access: Size: The Extended SMRAM register controls the configuration of Extended SMRAM Space. The Extended SMRAM (E_SMRAM) Memory provides a Write-Back cacheable SMRAM Memory Space ...
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Register Description 4.8.20 ERRSTS – Error Status Register (Device #0) Address Offset: Default Value: Access: Size: This register is used to report various error conditions via Hub Interface Special cycles. An SERR, SMI, or SCI Error Hub Interface Special cycle ...
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R 4.8.21 ERRCMD – Error Command Register (Device #0) Address Offset: Default Value: Access: Size: This register enables various errors to generate a SERR Hub Interface Special cycle. Since the GMCH does not have a SERR# signal, SERR messages are ...
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Register Description Bit 5 SERR on Receiving Unimplemented Special Cycle Hub Interface Completion Packet The GMCH generates an SERR Hub Interface Special cycle when a GMCH initiated Hub interface request is terminated with a Unimplemented Special cycle completion ...
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R 4.8.23 SCICMD – SCI Error Command Register (Device 0) Address Offset: Default Value: Access: Size: This register enables various errors to generate a SCI Hub Interface Special cycle. When an Error Flag is set in the ERRSTS register, it ...
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Register Description 4.8.24 SHIC – Secondary Host Interface Control Register (Device #0) Address Offset: Default Value: Access: Size: Bit 31 Reserved 30 BREQ0# Control of FSB Address and Control bus power management Disable FSB address and control bus ...
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R Bit AGP/DVO Mux Strap (Read only) 1 Specifies the use of AGP bus muxed with DVO. This bit is defined at Reset by a strap on the G_PAR/DVO_DETECT signal. By default the AGP bus pulls this signal high. The ...
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Register Description 4.8.26 AGPSTAT – AGP Status Register (Device #0) Address Offset: Default Value: Access: Size: This register reports AGP device capability/status. Bit 31:24 Request (RQ). Indicates a maximum of 32 outstanding AGP command requests can be handled by the ...
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R 4.8.27 AGPCMD – AGP Command Register (Device #0) Address Offset: Default Value: Access: Size: This register provides control of the AGP operational parameters. Bit 31:10 Reserved 9 Side Band Addressing Enable (SBA_EN). When this bit is set to 1, ...
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Register Description 4.8.28 AGPCTRL – AGP Control Register (Device #0) Address Offset: Default Value: Access: Size: This register provides for additional control of the AGP interface. Bit 7 is visible to the operating system and must be retained in this ...
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R Bit 2 AGP/PCI1 Discard Timer Disable Enable (default). Enables the Discard Timer for the delayed transactions on the PCI1/AGP interface (initiated by the AGP agent using PCI protocol). The counter starts once the delayed transaction request is ...
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Register Description 4.8.31 ATTBASE – Aperture Translation Table Base Register (Device #0) Address Offset: Default Value: Access: Size: This register provides the starting address of the Graphics Aperture Translation Table Base located in the main DDR SDRAM. This value is ...
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R 4.8.33 LPTT – Low Priority Transaction Timer Register (Device #0) Address Offset: Default Value: Access: Size: LPTT is an 8-bit register similar in a function to AMTT. This register is used to control the minimum tenure on the AGP ...
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... Register Description ® 4.9 Intel 855GM/GME GMCH Main Memory Control, Memory I/O Control Registers (Device #0, Function #1) The following table shows the GMCH Configuration Space for Device #0, Function #1. See Section 4.2f or access nomenclature. Table 27. Host-Hub I/F Bridge/System Memory Controller Configuration Space (Device #0, ...
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... The VID Register contains the vendor identification number. This 16-bit register combined with the Device Identification Register uniquely identifies any PCI device. Writes to this register have no effect. Bit 15:0 Vendor Identification (VID): This register field contains the PCI standard identification for Intel. 4.9.2 DID – Device Identification Register Address Offset: Default Value: ...
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... PCICMD – PCI Command Register Address Offset: Default Value: Access: Size: Since Intel chipset Device #0 does not physically reside on PCI_A, many of the bits are not implemented. Bit 15:10 Reserved 9 Fast Back-to-Back Enable (FB2B): This bit controls whether or not the master can do fast back-to- back Write ...
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R 4.9.4 PCISTS – PCI Status Register Address Offset: Default Value: Access: Size: PCISTS is a 16-bit status register that reports the occurrence of error events on Device #0’s PCI Interface. Bit 14 is Read/Write Clear. All other bits are ...
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... Address Offset: Default Value: Access: Size: This register contains the Base Class code of the Intel 855GM/GME GMCH Device #0 Function #1. This code is 08h indicating Other Peripheral device. Bit 7:0 Base Class Code (BASEC): This is an 8-bit value that indicates the Base Class Code for the GMCH. ...
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R 4.9.8 HDR – Header Type Register Address Offset: Default Value: Access: Size: This register identifies the header layout of the configuration space. No physical register exists at this location. Bit 7:0 PCI Header (HDR): This field always returns 80 ...
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Register Description 4.9.11 CAPPTR – Capabilities Pointer Register Address Offset: Default Value: Access: Size: The CAPPTR provides the offset that is the pointer to the location of the first device capability in the capability list. Bit 7:0 Pointer to the ...
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R 4.9.13 DRA – DRAM Row Attribute Register (Device #0) Address Offset: Default Value: Access: Size: The DDR SDRAM Row Attribute Register defines the page sizes to be used when accessing different pairs of Rows. Each Nibble of information in ...
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Register Description 4.9.14 DRT – DRAM Timing Register (Device #0) Address Offset: Default Value: Access: Size: This register controls the timing of the DDR SDRAM controller. Bit 31 DDR Internal Write to Read Command delay (tWTR): The tWTR is a ...
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R Bit 27:26 Back To Back Read-Write commands spacing (DDR, same or different Rows/Bank): This field determines the RD-WR command spacing, in terms of common clocks based on the following formula 0.5xBL + TA (RD-WR) – DQSS DQSS: ...
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Register Description Bit 14:12 Refresh Cycle Time (tRFC): Refresh Cycle Time is measured for a given row from REF command (to perform a refresh) until following ACT to same row (to perform a Read or Write tracked separately ...
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R Bit 3:2 DDR SDRAM RAS# to CAS# Delay (tRCD): This bit controls the number of clocks inserted between a Row Activate command and a Read or Write command to that row. Encoding 00: 01: 10: 11: 1:0 DDR SDRAM ...
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Register Description 4.9.15 PWRMG – DRAM Controller Power Management Control Register (Device #0) Address Offset: Default Value: Access: Size: Bit 31:24 Reserved 23:20 Row State Control: This field determines the number of clocks the System Memory Controller will remain in ...
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R Bit 11 Rcven DLL shutdown disable Normal operation. RCVEN DLL is turned off when the corresponding SO-DIMM is unpopulated RCVEN DLL is turned on irrespective of SO-DIMM population. 10 ECC SO-DIMM Clock tri-state Disable: 0 ...
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Register Description Bit 19:16 Reserved 15 RAS Lock-Out Enable: Set all populated rows support RAS Lock-Out. Defaults this bit is set the DDR SDRAM Controller assumes that the DDR SDRAM ...
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R Bit 011: Mode Register Set Enable – All CPU cycles to DDR SDRAM result in a Mode Register set command on the DDR SDRAM Interface. Host address lines are mapped to DDR SDRAM address lines in order to specify ...
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Register Description consumed during the sampling period. Although bandwidth from/to independent rows and GMCH Write bandwidth is measured independently, once Tripped all transactions except high priority graphics Reads are subject to throttling. Bit 31:28 DDR SDRAM Throttle Mode (TMODE): Four ...
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R Bit 27:24 Read Counter Based Power Throttle Control (RCTC): These bits select the Counter based Power Throttle Bandwidth Limits for Read operations to system memory. R/ Throttle Lock 85 70 65% ...
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Register Description Bit 19:16 Read Thermal Based Power Throttle Control (RTTC): These bits select the Thermal Sensor based Power Throttle Bandwidth Limits for Read operations to system memory. R/ Throttle Lock 85 70% 2h ...
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... Throttling is imposed. Note that programming this field to 00h disables system memory throttling. Recommended values are between 0.25 and 0.75 seconds. ® 4.10 Intel 855GM/GME GMCH Configuration Process Registers (Device #0, Function #3) See Section 4.2 for access nomenclature. Table 28 summarizes all Device#0, Function #3 registers. ...
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... PCICMD – PCI Command Register Address Offset: Default Value: Access: Size: Since Intel 855GM/GME GMCH Device #0 does not physically reside on PCI_A many of the bits are not implemented. Bit 15:10 Reserved 9 Fast Back-to-Back Enable (FB2B): This bit controls whether or not the master can do fast back-to- back Write ...
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R Bit 4 Memory Write and Invalidate Enable (MWIE): The GMCH will never issue Memory Write and Invalidate commands. This bit is therefore hardwired to 0. Writes to this bit position will have no effect. 3 Special Cycle Enable (SCE): ...
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... Address Offset: Default Value: Access: Size: This register contains the revision number of the Intel 855GM/GME GMCH. These bits are Read Only and Writes to this register have no effect. Bit 7:0 Revision Identification Number (RID): This is an 8-bit value that indicates the revision identification number for the GMCH ...
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R 4.10.8 HDR – Header Type Register Address Offset: Default Value: Access: Size: This register identifies the header layout of the configuration space. No physical register exists at this location. Bit 7:0 PCI Header (HDR): This field always returns 80 ...
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Register Description 4.10.11 CAPPTR – Capabilities Pointer Register Address Offset: Default Value: Access: Size: The CAPPTR provides the offset that is the pointer to the location of the first device capability in the capability list. Bit 7:0 Pointer to the ...
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... R ® Table 29. Intel 855GM GMCH Configurations and Some Resolution Examples Straps Read FSB System Through Rate Memory HPLLCC[2:0]: Frequency D0:F3:Regist er Offset C0- C1h, bits[2:0] 000 400 266 MHz MHz 001 400 200 MHz MHz 010 400 200 MHz MHz Datasheet GFX Core ...
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... Register Description ® Table 30. For Intel 855GME GMCH Configurations and Some Resolution Examples Straps Read FSB Through Rate Memory HPLLCC[2:0]: Frequency D0:F3:Register Offset C0-C1h, bits[2:0] 000 400 266 MHz MHz 001 400 200 MHz MHz 010 400 200 MHz MHz 111 ...
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... R ® 4.11 Intel 852GM GMCH Integrated Graphics Device Registers (Device #2, Function #0) This section contains the PCI configuration registers listed in order of ascending offset address. Device #2 incorporates Function #0. See Section 4.2 for access nomenclature. Note: C0F0 = Copy of Function #0 and U1F1 = Unique in Function #1. Table 31. Integrated Graphics Device Configuration Space (Device #2, Function#0) ...
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... The VID Register contains the vendor identification number. This 16-bit register combined with the Device Identification Register uniquely identifies any PCI device. Writes to this register have no effect. Bit 15:0 Vendor Identification Number: This is a 16-bit value assigned to Intel. 4.11.2 DID – Device Identification Register (Device #2) Address Offset: Default Value: ...
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R Bit Bus Master Enable (BME) ⎯R/W: This bit determines if the IGD is to function as a PCI compliant 2 master. 0= Disable IGD bus mastering (default Enable IGD bus mastering. Memory Access Enable (MAE) ⎯R/W: This ...
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Register Description 4.11.5 RID – Revision Identification Register (Device #2) Address Offset: Default Value: Access: Size: This register contains the revision number of the IGD. These bits are Read Only and Writes to this register have no effect. Bit 7:0 ...
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R 4.11.8 MLT – Master Latency Timer Register (Device #2) Address Offset: Default Value: Access: Size: The IGD does not support the programmability of the master latency timer because it does not perform bursts. Bit 7:0 Master Latency Timer Count ...
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Register Description 4.11.11 MMADR – Memory Mapped Range Address Register (Device #2) Address Offset: Default Value: Access: Size: This register requests allocation for the IGD registers and instruction ports. The allocation is for 512-kB and the base address is defined ...
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R 4.11.13 SVID – Subsystem Vendor Identification Register (Device #2) Address Offset: Default Value: Access: Size: Bit 15:0 Subsystem Vendor ID: This value is used to identify the vendor of the subsystem. This register should be programmed by BIOS during ...
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Register Description 4.11.16 INTRLINE – Interrupt Line Register (Device #2) Address Offset: Default Value: Access: Size: Bit 7:0 Interrupt Connection: Used to communicate interrupt line routing information. POST software Writes the routing information into this register as it initializes and ...
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R 4.11.20 PMCAP – Power Management Capabilities Register (Device #2) Address Offset: Default Value: Access: Size: Bit 15:11 PME Support: This field indicates the power states in which the IGD may assert PME#. Hardwired indicate that the ...
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Register Description 122 R Datasheet ...
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... BIOS and APIC memory space can be allocated. Figure 6 and Figure 7 depict the system memory address map in a simplified form and provide details on mapping specific system memory regions as defined and supported by the GMCH. Datasheet Intel® 855GM/GME GMCH System Address Map 123 ...
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... Intel® 855GM/GME GMCH System Address Map Figure 6. Simplified View of System Address Map 4 GB Top of the M ain Mem ory 0 124 PCI Mem ory Graphic Address Range ( Local) Memory Main Program mable Mem ory Address Range GMCH System Memory Space Independently Non-Overlapping ...
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... BIOS area There are 16 system memory segments in the compatibility area. Thirteen of the system memory ranges can be enabled or disabled independently for both Read and Write cycles. Datasheet Intel® 855GM/GME GMCH System Address Map 4 GB max TOM 0FFFFFh ...
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... Intel® 855GM/GME GMCH System Address Map Table 32. System Memory Segments and Their Attributes System Memory Segments 000000H - 09FFFFH 0A0000H - 0BFFFFH 0C0000H - 0C3FFFH 0C4000H - 0C7FFFH 0C8000H - 0CBFFFH 0CC000H - 0CFFFFH 0D0000H - 0D3FFFH 0D4000H - 0D7FFFH 0D8000H - 0DBFFFH 0DC000H - 0DFFFFH 0E0000H - 0E3FFFH 0E4000H - 0E7FFFH ...
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... PCI Memory space from the top of system memory with two specific ranges. • APIC Configuration Space from FEC0_0000h (4 GB–20 MB) to FECF_FFFFh (4 GB–19 MB -1) and FEE0_0000h (4 GB–18 MB) to FEEF_FFFFh (4 GB–17 MB-1). • High BIOS area from Datasheet Intel® 855GM/GME GMCH System Address Map 127 ...
Page 128
... Intel® 855GM/GME GMCH System Address Map 5.4 Main System Memory Address Range (0010_0000h to Top of Main Memory) The address range from the top of main system memory is mapped to main DDR SDRAM address range controlled by the GMCH. The GMCH will forward all accesses to addresses within this range to the DDR SDRAM unless a hole in this range is created using the fixed hole as controlled by the FDHC register ...
Page 129
... The second exception is addresses decoded to the system memory mapped range of the Internal Graphics device. One per function in device #2. Both exception cases are forwarded to the Internal Graphics device AGP configuration, there are two exceptions to this rule: Datasheet Intel® 855GM/GME GMCH System Address Map 129 ...
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... Intel® 855GM/GME GMCH System Address Map ⎯ Addresses decoded to the AGP Memory Window defined by the MBASE,MLIMIT,PMBASE, and PMLIMIT registers are mapped to AGP. ⎯ Addresses decoded to the Graphics Aperture range defined by the APBASE and APSIZE registers are mapped to the main DDR SDRAM. ...
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... These abbreviations are used later in Table 34. Table 34. SMM Space Transaction Handling SMM Space Enabled Compatible (C) High (H) TSEG (T) Datasheet Intel® 855GM/GME GMCH System Address Map Transaction Address Space (Adr) A0000h to BFFFFh 0FEDA0000h to 0FEDBFFFFh (TOM-TSEG_SZ) to TOM DRAM Space (DRAM) A0000h to BFFFFh A0000h to BFFFFh ...
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... Intel® 855GM/GME GMCH System Address Map 5.4.4 System Memory Shadowing Any block of system memory that can be designated as Read-Only or Write-Only can be “shadowed” into GMCH DDR SDRAM. Typically this is done to allow ROM code to execute more rapidly out of main DDR SDRAM. ROM is used as a Read-Only during the copy process while DDR SDRAM at the same time is designated Write-Only ...
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... For Reads and for Writes requiring completion, the GMCH will provide separate completion status for each naturally aligned 32-B or 64-B block. If the starting address of a transaction hits a valid address, the portion of a request that hits that Datasheet Intel® 855GM/GME GMCH System Address Map 133 ...
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... Intel® 855GM/GME GMCH System Address Map target device (DDR SDRAM) will complete normally. The remaining portion of the access that crosses a device boundary (targets a different device than that of the starting address) or hits an invalid address will be remapped to system memory address 0h, snooped on the Host Bus, and dispatched to DDR SDRAM. Reads will return all 1’ ...
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... IAAF error flag. The portion of a write access that hits an invalid address will be remapped to memory address 0h with BE’s deasserted (effectively dropped “on the floor”) and set the IAAF error flag. Datasheet Intel® 855GM/GME GMCH System Address Map § 135 ...
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... Intel® 855GM/GME GMCH System Address Map 136 R Datasheet ...
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... System Bus Interrupt Delivery The Intel Pentium M processor and Intel Celeron M processor support system bus interrupt delivery. It does not support the APIC serial bus interrupt delivery mechanism. Interrupt related messages are encoded on the system bus as Interrupt Message transactions. System bus interrupts may originate from the processor on the system bus, or from a downstream device on the Hub interface ...
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Functional Description In a GMCH platform, the ICH4-M contains IOxAPICs and its interrupts are generated as upstream Hub interface Memory Writes. Furthermore, PCI 2.2 defines MSI’s (Message Signaled Interrupts) that are also in the form of Memory Writes. A PCI ...
Page 139
... GMCH system memory interface. For SMBus Configuration and Access of the Serial Presence Detect Ports, refer to the Intel® 82801DBM I/O Controller Hub 4 Mobile (ICH4-M) Datasheet (252337) for more details. ...
Page 140
... Qword of memory. It then checks the code for reads from memory but does not correct any errors that are found. 6.4 Integrated Graphics Overview The Intel 855GM/855GME GMCH provides a highly integrated graphics accelerator and PCI set while allowing a flexible Integrated System Graphics solution. Note: Intel 855GME GMCH can support an AGP discrete graphics controller. 140 ...
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... R ® Figure 8. Intel 855GM GMCH Graphics Block Diagram (MPEG2 Decode) Instr./ Data High bandwidth access to data is provided through the system memory port. The GMCH uses a tiling architecture to minimize page miss latencies and thus maximize effective rendering bandwidth. 6.4.1 3D/2D Instruction Processing The GMCH contains an extensive set of instructions that control various functions including 3D rendering, BLT operations, display, MPEG decode acceleration, and overlay ...
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... This method also creates a smooth motion of texture as it traverses across the display. 6.4.2.2 Video Mixer Rendering (Intel VMR refers to the ability to blend any data format/source with other displayable content. It allows 3D, video/DVD, 2D bitmap and closed caption to be mixed together. VMR works mainly as a front-end processor, thereby reducing dependence on video ports and overlays 6 ...
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... The GMCH, using Intel’s Direct Memory Execution model, simplifies this process by rendering each scene using the texture located in system memory. The GMCH includes a cache controller to avoid frequent memory fetches of recently used texture data ...
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Functional Description 6.4.2.10 Perspective Correct Texture Support A textured polygon is generated by mapping a 2D texture pattern onto each pixel of the polygon. A texture map is like wallpaper pasted onto the polygon. Since polygons are rendered in perspective, ...
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R 6.4.2.14 Texture Map Filtering Many texture-mapping modes are supported. Perspective correct mapping is always performed. As the map is fitted across the polygon, the map can be tiled, mirrored in either the directions, or mapped up ...
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Functional Description Flexible vertex format support allows multi-texturing because it makes it possible to pass more than one texture in the vertex structure. 6.4.2.16 Cubic Environment Mapping Environment maps allow applications to render scenes with complex lighting and reflections while ...
Page 147
R 6.4.3.3 Color Shading Modes The Raster engine supports the Flat and Gouraud shading modes. These shading modes are programmed by the appropriate state variables issued through the command stream. • Flat shading is performed by smoothly interpolating the vertex ...
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Functional Description 6.4.3.7 Color Buffer Formats: (Destination Alpha) The Raster engine supports 8-bit, 16-bit, and 32-bit Color Buffer formats. The 8-bit format is used to support planar YUV4:2:0 format, which is used only in Motion Compensation and Arithmetic Stretch format. ...
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R test. The selection of the stencil operation to be performed is based upon the result of the stencil test and the depth test. A stencil write mask is also included that controls the writing of particular bits into the ...
Page 150
... The analog display port may only use Pipe A or Pipe B, the DVO ports may use either Pipe A or Pipe B, and the Internal LVDS interface may only use Pipe B. This limits the resolutions available on a digital display when an analog CRT is active. Table 37. Dual Display Usage Model (Intel Display Pipe A DVO Both ...
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R 6.4.6.1 Cursor Color Formats Color data can indexed format or a true color format. Indexed data uses the entries in the four-entry cursor palette to convert the two-bit index to a true color format before being ...
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Functional Description 6.4.7.3 Gamma Correction To compensate for overlay color intensity loss, the overlay engine supports independent gamma correction. This allows the overlay data to be converted to linear data or corrected for the display device when not blending. 6.4.7.4 ...
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R 6.4.8.2 Hardware Motion Compensation The HWMC process consists of reconstructing a new picture by predicting (either forward, backward, or bi-directional) the resulting pixel colors from one or more reference pictures. The GMCH receives the video stream and implements Motion ...
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Functional Description 6.5.1.1 Integrated RAMDAC The display function contains a 350 MHz, integrated, 24-bit, RAM-based Digital-to-Analog Converter (RAMDAC) that transforms up to 2048X1536 digital pixels at a maximum refresh rate of 75 Hz. Three, 8-bit DACs provide the R, G, ...
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R 6.5.2.2 LVDS Interface Signals LVDS for flat panel is compatible with the ANSI/TIA/EIA-644 specification. This is an electrical standard only defining driver output characteristics and receiver input characteristics. There are two LVDS transmitter channels (channel A and channel B) ...
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Functional Description 6.5.2.7 Panel Power Sequencing This section provides details for the power sequence timing relationship of the panel power, the backlight enable and the LVDS data timing delivery. In order to meet the panel power timing specification requirements, two ...
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R Table 38. Panel Power Sequencing Timing Parameters Name T1+T2 Vdd On to LVDS Active Panel Vdd must be on for a minimum time before the LVDS data stream is enabled. T5 Backlight LVDS data must be enabled for a ...
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... Optionally the FIELD pin can indicate to the overlay which field is currently being displayed at the display device. 6.5.2.10 Intel 855GME GMCH AGP Interface Overview The GMCH support 1.5 V AGP 1X/2X/4X devices. The AGP signal buffers are 1.5 V drive/receive (buffers are not 3.3 V tolerant). The GMCH support 2X/4X source synchronous clocking transfers for read and write data, and sideband addressing ...
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R AGP Command Hi-Priority Long Read Flush Reserved Fence Reserved Reserved Reserved NOTE: N/A refers to a function that is not applicable target of an AGP cycle, the GMCH supports all the transactions targeted at main memory (summarized ...
Page 160
Functional Description The 4X data rate transfer provides 1.06 GB/s transfer rates. The control signal protocol for the 4X data transfer protocol is identical to 1X/2X protocol mode 16 bytes of data are transferred on every 66 MHz ...
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R Table 41. PCI Commands Supported by the GMCH When Acting as a FRAME# Target PCI Command Interrupt Acknowledge Special Cycle I/O Read I/O Write Reserved Reserved Memory Read Memory Write Reserved Reserved Configuration Read Configuration Write Memory Read Multiple ...
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Functional Description • Fast Back-to-Back Transactions. GMCH as a target supports fast back-to-back cycles from an AGP FRAME# initiator initiator of AGP FRAME# cycle, the GMCH only supports the following transactions: • Memory Read and Memory Read Line. ...
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R 6.5.6 Concurrent and Simultaneous Display The GMCH has two independent pipes, each with its own timing generator and dot clock, and thus is able to support two displays concurrently. Windows 98* and Windows 2000* have enabled support for multi-monitor ...
Page 164
Functional Description 164 R Datasheet ...
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... System memory Self-Refresh in C3 state (Intel 855GME GMCH) • Enhanced Intel SpeedStep technology (using Intel Pentium M processor) • Flat Panel Power Sequencing • Intel 855GM/GME GMCH reduces I/O power dynamically by disabling sense amps on the input buffers, as well as tri-stating the output buffers when possible 7.1 General Description of Supported CPU States C0 (Full On): This is the only state that runs software ...
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... C4 (Deeper Sleep): The C4 state appears to the GMCH as identical to the C3 state, but in this state the processor core voltage is lowered. There are no internal events in GMCH for the C4 state that differ from the C3 state. (C4 state not supported by Intel Celeron M processor) 7.2 7.2. General Description of ACPI States • ...
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... DIMM (or any other appropriate platform location remote Thermal Diode may be placed next to the SO-DIMM (or any other appropriate platform location) and connected to the External Thermal sensor. Intel advises that the External Thermal sensor contains some form of hysteresis, since none is provided by the GMCH hardware. ...
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... GMCH-based Read Throttle will apply equally. Note: The use of external sensors that include an internal pull-up resistor on the open-drain Thermal trip output is discouraged. However, it may be possible depending on the size of the pull-up and the voltage of the sensor. Please refer to the Intel Processor, and Intel 7.5.1 ...
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... Electrical Characteristics 8.1 Absolute Maximum Ratings Table 43 lists the Intel 855GM/855GME GMCH maximum environmental stress ratings. Functional operation at the absolute maximum and minimum is neither implied nor guaranteed. Functional operating parameters are listed in the AC and DC tables. Warning: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage. ...
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... Please refer to the Intel® 852GM/855GM/855GME Chipset Mobile Thermal Design Guide for supplementary details. 2. Possible damage to the GMCH may occur if the GMCH temperature exceeds 150 °C. Intel does not guarantee functionality for parts that have exceeded temperatures above 150 °C due to spec violation ...
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... V DDR SDRAM System Memory VCCSM Data Buffer Supply Current (DDR266 SDRAM) 2.5 V DDR SDRAM System Memory Data Buffer Supply Current (DDR333 SDRAM for Intel 855GME GMCH only) I 1.2 V DDR SDRAM System Memory VCCASM DLL Supply Current (DDR266 SDRAM) Datasheet Parameter Min < ...
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... It is based on extrapolations in both hardware and software technology over the life of the component. It does not represent the expected power generated by a power virus. Studies by Intel indicate that no application will cause thermally significant power dissipation exceeding this specification, although it is possible to concoct higher power synthetic workloads that write but never read ...
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R Table 46. Table Signals Signal Signal Type Group Host Interface Signal Groups (a) Input/Outputs (b) Common Clock (d) Host Miscellaneous (c) Asynchronous Input DVO Signal Groups (e) (f) (e),(f) DDC/I2C Input/Output (g) DVO Miscellaneous AGP Signal Groups (m1) (m2) ...
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... Clock Inputs (u) Clock Outputs (w) Clock Inputs (x) Clock Outputs (z) Low Voltage Differential (a1) (b1) Clock Outputs I/O Buffer Supply Voltages/Grounds (Intel 855GME GMCH Only) (n1) (p1) Hub Interface (s1) 174 CMOS HL[10:0], HLSTB, HLSTB# Analog/Ref HLRCOMP, PSWING, HLVREF SSTL_2 SDQ[63:0], SDQS[7:0] SSTL_2 SCS[3:0]#, SMA[12:0], SBA[1:0], SRAS#, SCAS#, SWE#, ...
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... R Signal Signal Type Group (q1) DDR SDRAM DLL I/O Buffer Supply Voltages/Grounds (Intel 855GM/855GME GMCH Common) (m1) Power Supply (d1) (e1) Hub Interface (f1) (g1) DDR SDRAM Supply (g1) DDR SDRAM DLL (h1) DVO Supply (i1) DAC Supply (j1) GPIO Supply (k1) LVDS Digital Supply (k1) LVDS Data/CLK Transmitter Supply (k1) ...
Page 176
... DC Characteristics 8.5.1 General DC Characteristics Table 47. DC Characteristics Symbol Supply Voltages (Intel 855GME GMCH Only) VCC VCCHL VCCASM VCCAGPLL VCCAHPLL VCCADPLLA VCCADPLLB Supply Voltages (Intel 855GM/855GME GMCH Common) VTTLF VCCSM VCCQSM VCCASM VCCHL VCCAGPLL VCCAHPLL VCCADPLLA VCCADPLLB VCC VCCDVO VCCDLVDS VCCTXLVDS ...
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R Symbol VCCALVDS VCCADAC VCCGPIO Reference Voltages HAVREF HDVREF[2:0] HCCVREF HXSWING HYSWING HLVREF SMVREF_0 GVREF PSWING SMVSWINGH Datasheet Signal Parameter Min Group (k1) Analog LVDS 1.425 Supply Voltage (i1) DAC Supply 1.425 Voltage (j1) CMOS 3.135 Supply Voltage (d) Host ...
Page 178
Electrical Characteristics Symbol SMVSWINGL Host Interface V IL_H V IH_H V OL_H V OH_H I OL_H I LEAK_H C PAD C PCKG DDR Interface V IL(DC) V IH(DC) V IL(AC) 178 Signal Parameter Min Group (p) System (VCCSM Memory * ...
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R Symbol V IH(AC Leak C PAD C PCKG 1.5V AGP Interface V IL_A V IH_A V OL_A V OH_A I OL_A I OH_A I LEAK_A C PAD C PCKG Datasheet ...
Page 180
Electrical Characteristics Symbol 1.5 V DVO Interface: Functional Operating Range (VCC=1.5 V± 5%) V IL_DVO V IH_DVO V OL_DVO V OH_DVO I OL_DVO I OH_DVO I LEAK_DVO C PAD C PCKG 1.2 V & 1.35 V Hub Interface V IL_HI ...
Page 181
R Symbol C PAD C PCKG LVDS Interface: Functional Operating Range (VCC=2.5 V±5 ∆ ∆ Miscellaneous Signals Datasheet ...
Page 182
Electrical Characteristics Symbol I LEAK Cpad C PCKG C PAD C PCKG CROSS C PAD C PCKG V IL 182 Signal Parameter Min Group (q) Input Leakage Current (CMOS Inputs) (a1) Input 1 Capacitance (LVTTL ...
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... Defined for a double 75- termination. 5. Set by external reference resistor value. 6. INL and DNL measured and calculated according to VESA Video Signal Standards. 7. Max full-scale voltage difference among R,G,B outputs (percentage of steady-state full-scale voltage) ® Note: Refer to the Intel Pentium Guide for interconnect length specifications. Datasheet Signal ...
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Electrical Characteristics 8.5.3 DAC Reference and Output Specifications Table 49. DAC Reference and Output Specifications Parameter Reference resistor R,G,B termination resistor Video Filter Ferrite Bead Video Filter Capacitors NOTES: 1. VESA Video Signal Standard 2. Complement DAC channel output termination ...
Page 185
... PI Configuration (One PI Filter Testability) In the Intel 855GM/GME GMCH, testability for automated test equipment (ATE) board level testing has been implemented as an XOR chain. An XOR-tree is a chain of XOR gates, each with one input pin connected to it. The XOR Chain test mode is used by product engineers during manufacturing and OEMs during board level connectivity tests ...
Page 186
Video Filter Capacitors and Ferrite Bead Arranged Configuration (One PI Filter Testability) 9.1 XOR Test Mode Entry Figure 11. XOR Chain Test Mode Entry Events Diagram ...
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R 9.2 XOR Chain Differential Pairs Table 50 provides differential signals in the XOR chains that must be treated as pairs. Pin1 and Pin2 as shown below need to drive to the opposite value always. Table 50. Differential Signals in ...
Page 188
... 9.4 XOR Chain Connectivity/Ordering The following tables contain the ordering for all of the Intel 855GM/GME GMCH XOR chains and pin to ball mapping information: Table 52. XOR Mapping XOR Chain DVO 1 DVO IN/OUT XOR Out 1 INOUT 2 INOUT 3 INOUT 4 INOUT 5 INOUT 6 INOUT 7 INOUT 8 INOUT ...
Page 189
R 10 INOUT 11 INOUT 12 INOUT 13 INOUT 14 INOUT 15 INOUT 16 INOUT 17 INOUT 18 INOUT 19 INOUT 20 INOUT 21 INOUT 22 INOUT 23 INOUT 24 INOUT 25 INOUT 26 INOUT 27 28 XOR Chain DVO ...
Page 190
Video Filter Capacitors and Ferrite Bead Arranged Configuration (One PI Filter Testability) 16 INOUT 17 INOUT 18 INOUT 19 INOUT 20 INOUT ...
Page 191
R 14 INOUT 15 INOUT 16 INOUT 17 INOUT 18 INOUT 19 INOUT 20 INOUT 21 INOUT 22 INOUT 23 INOUT 24 INOUT 25 INOUT 26 INOUT 27 INOUT 28 INOUT 29 INOUT 30 INOUT 31 INOUT 32 INOUT 33 ...
Page 192
Video Filter Capacitors and Ferrite Bead Arranged Configuration (One PI Filter Testability) 6 INOUT 7 INOUT 8 INOUT 9 INOUT 10 INOUT 11 INOUT 12 INOUT 13 INOUT 14 INOUT 15 INOUT 16 INOUT 17 INOUT 18 ...
Page 193
R XOR Chain FSB 3 IN/OUT XOR Out INOUT 4 INOUT 5 INOUT 6 INOUT 7 8 INOUT 9 10 INOUT 11 INOUT 12 INOUT 13 INOUT 14 INOUT 15 INOUT 16 INOUT 17 INOUT 18 INOUT ...
Page 194
Video Filter Capacitors and Ferrite Bead Arranged Configuration (One PI Filter Testability) 35 INOUT 36 INOUT 37 INOUT 38 INOUT 39 INOUT 40 INOUT 41 INOUT 42 INOUT 43 INOUT 44 INOUT 45 INOUT XOR Chain GPIO ...
Page 195
XOR Chain LVDS XOR Out XOR Chain SM1 XOR Out 1 2 ...
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Video Filter Capacitors and Ferrite Bead Arranged Configuration (One PI Filter Testability ...
Page 197
Datasheet Video ...
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Video Filter Capacitors and Ferrite Bead Arranged Configuration (One PI Filter Testability) 42 XOR Chain SM 3 DDR SDRAM IN/OUT XOR Out 1 2 INOUT 3 INOUT 4 INOUT 5 INOUT 6 INOUT 7 INOUT 8 INOUT ...
Page 199
R 34 INOUT 35 INOUT 36 INOUT 37 INOUT 38 INOUT 39 INOUT 40 INOUT 41 INOUT 42 INOUT 43 INOUT 44 INOUT 45 INOUT 46 INOUT 47 INOUT 48 INOUT 49 INOUT Datasheet Video Filter Capacitors and Ferrite Bead ...
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Video Filter Capacitors and Ferrite Bead Arranged Configuration (One PI Filter Testability) 9.4.1 VCC/VSS Voltage Groups Table 53. Voltage Levels and Ball Out for Voltage Groups Name Voltage Level VCC 1.2 (855GM) 1.35 (855GME) VCCADAC 1.5 VCCDVO ...