JG82855GME S L7VN Intel, JG82855GME S L7VN Datasheet - Page 32

• Manufacturer Part Number: JG82855GME S L7VN
• Manufacturer: Intel

Specifications of JG82855GME S L7VN

• Package Type: FCBGA
• Rad Hardened: No
• Lead Free Status / Rohs Status: Compliant

32
Signal Descriptions
3.2
RS[2:0]#
SCS[3:0]#
SMA[12:0]
SBA[1:0]
SRAS#
SCAS#
SWE#
SDQ[71:0]
Table 4. DDR SDRAM Interface Descriptions
Signal Name
Signal Name
DDR SDRAM Interface
SSTL_2
SSTL_2
SSTL_2
SSTL_2
SSTL_2
SSTL_2
SSTL_2
AGTL+
Type
Type
I/O
O
O
O
O
O
O
O
Chip Select: These pins select the particular DDR SDRAM components during the
active state.
NOTE: There is one SCS# per DDR-SDRAM Physical SO-DIMM device row. These
signals can be toggled on every rising System Memory Clock edge (SCMDCLK).
Multiplexed Memory Address: These signals are used to provide the multiplexed row
and column address to the DDR SDRAM.
Bank Select (Memory Bank Address): These signals define which banks are selected
within each DDR SDRAM row. The SMA and SBA signals combine to address every
possible location within a DDR SDRAM device.
DDR Row Address Strobe: SRAS# may be heavily loaded and requires tw0 DDR
SDRAM clock cycles for setup time to the DDR SDRAMs. Used with SCAS# and SWE#
(along with SCS#) to define the system memory commands.
DDR Column Address Strobe: SCAS# may be heavily loaded and requires two clock
cycles for setup time to the DDR SDRAMs. Used with SRAS# and SWE# (along with
SCS#) to define the system memory commands.
Write Enable: Used with SCAS# and SRAS# (along with SCS#) to define the DDR
SDRAM commands. SWE# is asserted during writes to DDR SDRAM. SWE# may be
heavily loaded and requires two clock cycles for setup time to the DDR SDRAMs.
Data Lines: These signals are used to interface to the DDR SDRAM data bus.
NOTE: ECC error detection is supported: by the SDQ[71:64] signals.
Response Status: Indicates the type of response according to the following the table:
RS[2:0]#
000
001
010
011
100
101
110
111
Response type
Idle state
Retry response
Deferred response
Reserved (not driven by GMCH)
Hard Failure (not driven by GMCH)
No data response
Implicit Write back
Normal data response
Description
Description
Datasheet
R