JG82855GME S L7VN Intel, JG82855GME S L7VN Datasheet - Page 6

• Manufacturer Part Number: JG82855GME S L7VN
• Manufacturer: Intel

Specifications of JG82855GME S L7VN

• Package Type: FCBGA
• Rad Hardened: No
• Lead Free Status / Rohs Status: Compliant

6
5
6
Intel
5.1
5.2
5.3
5.4
Functional Description .................................................................................................... 137
6.1
6.2
6.3
6.4
®
855GM/GME GMCH System Address Map .......................................................... 123
System Memory Address Ranges...................................................................... 123
DOS Compatibility Area ..................................................................................... 125
Extended System Memory Area......................................................................... 127
Main System Memory Address Range (0010_0000h to Top of Main Memory). 128
Host Interface Overview ..................................................................................... 137
Dynamic Bus Inversion....................................................................................... 137
System Memory Interface .................................................................................. 138
Integrated Graphics Overview............................................................................ 140
4.11.21 PMCS – Power Management Control/Status Register (Device #2) ... 121
5.4.1
5.4.2
5.4.3
5.4.4
5.4.5
5.4.6
5.4.7
6.2.1
6.2.2
6.3.1
6.3.2
6.3.3
6.4.1
6.4.2
15-MB – 16-MB Window..................................................................... 128
Pre-allocated System Memory............................................................ 128
5.4.2.1
5.4.2.2
5.4.2.3
5.4.2.4
5.4.2.5
5.4.2.6
5.4.2.7
System Management Mode (SMM) Memory Range .......................... 130
5.4.3.1
5.4.3.2
System Memory Shadowing ............................................................... 132
I/O Address Space.............................................................................. 132
5.4.5.1
GMCH Decode Rules and Cross-Bridge Address Mapping............... 133
Hub Interface Decode Rules............................................................... 133
5.4.7.1
5.4.7.2
System Bus Interrupt Delivery ............................................................ 137
Upstream Interrupt Messages ............................................................ 138
DDR SDRAM Interface Overview ....................................................... 138
System Memory Organization and Configuration............................... 139
6.3.2.1
6.3.2.2
DDR SDRAM Performance Description ............................................. 140
6.3.3.1
3D/2D Instruction Processing ............................................................. 141
3D Engine ........................................................................................... 141
6.4.2.1
6.4.2.2
6.4.2.3
6.4.2.4
6.4.2.5
6.4.2.6
6.4.2.7
Extended SMRAM Address Range (HSEG and TSEG) ... 129
HSEG ................................................................................ 129
TSEG ................................................................................. 129
Dynamic Video Memory Technology (DVMT)................... 129
PCI Memory Address Range (Top of Main System Memory
to 4 GB) ............................................................................. 129
APIC Configuration Space (FEC0_0000h -FECF_FFFFh,
FEE0_0000h- FEEF_FFFFh) ............................................ 130
High BIOS Area (FFE0_0000h -FFFF_FFFFh)................. 130
SMM Space Restrictions ................................................... 131
SMM Space Definition ....................................................... 131
AGP/PCI I/O Address Mapping ......................................... 132
Hub Interface Accesses to GMCH that Cross Device
Boundaries ........................................................................ 133
AGP Interface Decode Rules ............................................ 134
Configuration Mechanism for SO-DIMMs ......................... 139
System Memory Register Programming ........................... 139
Data Integrity (ECC) .......................................................... 140
Bi-Cubic Filtering (Intel
Video Mixer Rendering (Intel
Setup Engine ..................................................................... 142
Viewport Transform and Perspective Divide ..................... 142
3D Primitives and Data Formats Support.......................... 143
Pixel Accurate Fast Scissoring and Clipping Operation.... 143
Backface Culling................................................................ 143
®
855GME GMCH)........................ 142
®
855GME GMCH) .............. 142
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