MAX19711ETN+T Maxim Integrated Products, MAX19711ETN+T Datasheet - Page 8

• Manufacturer Part Number: MAX19711ETN+T
• Description: IC ANLG FRNT END 56-TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX19711ETN+T

• Number Of Bits: 10
• Number Of Channels: 2
• Power (watts): 37.5mW
• Voltage - Supply, Analog: 3V
• Voltage - Supply, Digital: 3V
• Package / Case: 56-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10-Bit, 11Msps, Full-Duplex
Analog Front-End
ELECTRICAL CHARACTERISTICS (continued)
(V
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, V
DAC output, C
values are at T
8
Idle Wake-Up Time (With CLK)
Standby Wake-Up Time
Enable Time from Tx to Rx,
Fast Mode
E nab l e Ti m e fr om Rx to Tx,
Fast M od e
Enable Time from Tx to Rx,
Slow Mode
E nab l e Ti m e fr om Rx to Tx,
S l ow M od e
INTERNAL REFERENCE (V
Positive Reference
Negative Reference
Common-Mode Output Voltage
Maximum REFP/REFN/COM
Source Current
Maximum REFP/REFN/COM
Sink Current
Differential Reference Output
Differential Reference Temperature
Coefficient
DD
_______________________________________________________________________________________
= 3V, OV
PARAMETER
A
REFP
DD
= +25°C.) (Note 1)
= 1.8V, internal reference (1.024V), C
= C
REFN
= C
REFIN
COM
= V
= 0.33µF, C
t
t
t
t
t
t
ENABLE,RX
ENABLE,RX
SYMBOL
ENABLE,TX
ENABLE,TX
DD
WAKE,ST0
WAKE,ST1
I
SOURCE
REFTC
V
I
V
; V
SINK
COM
REF
REFP
L
, V
< 5pF on all aux-DAC outputs, T
Fr om i d l e to Rx m od e w i th C LK p r esent
d ur i ng i d l e, AD C settl es to w i thi n 1d B S IN AD
From idle to Tx mode with CLK present
during idle, DAC settles to 10 LSB error
From idle to FD mode, ADC settles to
within 1dB SINAD, DAC settles to within 10
LSB error
From standby to Rx mode, ADC settles to
within 1dB SINAD
From standby to Tx mode, DAC settles to
10 LSB error
From standby to FD mode, ADC settles to
within 1dB SINAD, DAC settles to within 10
LSB error
ADC settles to within 1dB SINAD
DAC settles to within 10 LSB error
ADC settles to within 1dB SINAD
DAC settles to within 10 LSB error
V
V
V
REFN
REFP
REFN
REFP
L
≈ 10pF on all digital outputs, f
, V
- V
- V
- V
FS
COM
COM
REFN
COM
= 410mV, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx
levels are generated internally)
CONDITIONS
A
= T
CLK
MIN
= 11MHz (50% duty cycle), Rx ADC input
to T
V
+0.490
MAX
- 0.15
DD
MIN
, unless otherwise noted. Typical
/ 2
V
+0.512 +0.534
-0.256
0.256
TYP
21.8
21.8
DD
±30
6.8
5.0
6.8
7.2
0.1
6.8
1
5
2
2
/ 2
V
+ 0.15
MAX
DD
/ 2
ppm/°C
UNITS
mA
mA
µs
µs
µs
µs
µs
µs
V
V
V
V