MAX19711ETN+T Maxim Integrated Products, MAX19711ETN+T Datasheet

MAX19711ETN+T

Manufacturer Part Number

MAX19711ETN+T

Description

IC ANLG FRNT END 56-TQFN

Manufacturer

Maxim Integrated Products

Datasheet

1.MAX19711ETN.pdf (36 pages)

Specifications of MAX19711ETN+T

Number Of Bits

Number Of Channels

Power (watts)

37.5mW

Voltage - Supply, Analog

Voltage - Supply, Digital

Package / Case

56-TQFN Exposed Pad

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

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The MAX19711 is an ultra-low-power, highly integrated

mixed-signal analog front-end (AFE) ideal for CDMA

communication applications operating in full-duplex

(FD) mode. Optimized for high dynamic performance

and ultra-low power, the device integrates a dual 10-bit,

11Msps receive (Rx) ADC; dual 10-bit, 11Msps transmit

(Tx) DAC with CDMA baseband filters; three fast-settling

12-bit aux-DAC channels for ancillary RF front-end con-

trol; and a 10-bit, 333ksps housekeeping aux-ADC. The

typical operating power in FD mode is 37.5mW/42.7mW

at a 4.915MHz/11MHz clock frequency.

The Rx ADCs feature 54.8dB SNR and 74.2dBc SFDR at

1.875MHz input frequency with an 11MHz clock frequen-

cy. The analog I/Q input amplifiers are fully differential

and accept 1.024V

channel matching is ±0.01° phase and ±0.01dB gain.

The Tx DACs with CDMA lowpass filters feature -3dB

cutoff frequency of 1.3MHz and > 64dBc stopband

rejection at f

analog I-Q full-scale output voltage range is selectable at

±410mV or ±500mV differential. The output DC common-

mode voltage is selectable from 0.86V to 1.36V. The I/Q

channel offset is adjustable to optimize radio lineup side-

band/carrier suppression. Typical I-Q channel matching

is ±0.03dB gain and ±0.07° phase.

Two independent 10-bit parallel, high-speed digital

buses used by the Rx ADC and Tx DAC allow full-

duplex operation for frequency-division duplex applica-

tions. The Rx ADC and Tx DAC can be disabled

independently to optimize power management. A 3-wire

serial interface controls power-management modes, the

aux-DAC channels, and the aux-ADC channels.

The MAX19711 operates on a single 2.7V to 3.3V analog

supply and 1.8V to 3.3V digital I/O supply. The

MAX19711 is specified for the extended (-40°C to

+85°C) temperature range and is available in a 56-pin,

thin QFN package. The Selector Guide at the end of the

data sheet lists other pin-compatible versions in this AFE

family. For time-division duplex (TDD) applications, refer

to the MAX19705–MAX19708 AFE family of products.

*All devices are specified over the -40°C to +85°C operating range.

**EP = Exposed paddle.

19-0527; Rev 0; 5/06

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

CDMA Handsets

CDMA Data Cards

MAX19711ETN

MAX19711ETN+

PART*

IMAGE

________________________________________________________________ Maxim Integrated Products

= 4.285MHz at f

P-P

56 Thin QFN-EP**

Ordering Information

PIN-PACKAGE

+Denotes lead-free package.

General Description

full-scale signals. Typical I/Q

Portable Communication

Equipment

CLK

Applications

= 4.915MHz. The

PKG CODE

T5677-1

10-Bit, 11Msps, Full-Duplex

♦ Dual 10-Bit, 11Msps Rx ADC and Dual 10-Bit,

♦ Ultra-Low Power

♦ Integrated CDMA Filters with > 64dBc Stopband

♦ Programmable Tx DAC Common-Mode DC Level

♦ Excellent Dynamic Performance

♦ Three 12-Bit, 1µs Aux-DACs

♦ 10-Bit, 333ksps Aux-ADC with 4:1 Input Mux and

♦ Excellent Gain/Phase Match

♦ Multiplexed Parallel Digital I/O

♦ Serial-Interface Control

♦ Versatile Power-Control Circuits

♦ Miniature 56-Pin Thin QFN Package

Functional Diagram and Selector Guide appear at end of

data sheet.

11Msps Tx DAC

Rejection

and I/Q Offset Trim

Data Averaging

(7mm x 7mm x 0.8mm)

TOP VIEW

37.5mW/42.7mW at f

FD Mode

24.3mW at f

34.5mW at f

Low-Current Standby and Shutdown Modes

SNR = 54.8dB at f

SFDR = 75dBc at f

±0.01° Phase, ±0.01dB Gain (Rx ADC) at

Shutdown, Standby, Idle, Tx/Rx Disable

REFIN

ADC1

DAC3

DAC2

DAC1

REFN

COM

= 1.87MHz

GND

QDN

QDP

IDN

IDP

42 41 40 39 38 37 36 35 34 33 32 31 30 29

Analog Front-End

NOTE: THE PIN 1 INDICATOR IS “+” FOR LEAD-FREE DEVICES.

CLK

= 11MHz, Slow Rx Mode

= 11MHz, Slow Tx Mode

EXPOSED PADDLE (GND)

OUT

THIN QFN

MAX19711

= 1.875MHz (Rx ADC)

CLK

Pin Configuration

= 620kHz (Tx DAC)

= 4.915MHz/11MHz,

9 10 11 12 13 14

Features

DA3

DA2

DA1

DA0

OGND

AD9

AD8

AD7

AD6

AD5

AD4

AD3

AD2

Related parts for MAX19711ETN+T

MAX19711ETN+T Summary of contents

Page 1

... Thin QFN-EP** *All devices are specified over the -40°C to +85°C operating range. **EP = Exposed paddle. +Denotes lead-free package. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 10-Bit, 11Msps, Full-Duplex ♦ ...

Page 2

Full-Duplex Analog Front-End ABSOLUTE MAXIMUM RATINGS GND OGND ..............................-0.3V to +3.6V GND to OGND.......................................................-0.3V to +0.3V IAP, IAN, QAP, QAN, IDP, IDN, QDP, QDN, DAC1, DAC2, DAC3 to GND .....................-0. ...

Page 3

ELECTRICAL CHARACTERISTICS (continued 3V 1.8V, internal reference (1.024V amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, V DAC output 0.33µF, C REFP REFN COM values are ...

Page 4

Full-Duplex Analog Front-End ELECTRICAL CHARACTERISTICS (continued 3V 1.8V, internal reference (1.024V amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, V DAC output 0.33µF, C ...

Page 5

ELECTRICAL CHARACTERISTICS (continued 3V 1.8V, internal reference (1.024V amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, V DAC output 0.33µF, C REFP REFN COM values are ...

Page 6

Full-Duplex Analog Front-End ELECTRICAL CHARACTERISTICS (continued 3V 1.8V, internal reference (1.024V amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, V DAC output 0.33µF, C ...

Page 7

ELECTRICAL CHARACTERISTICS (continued 3V 1.8V, internal reference (1.024V amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, V DAC output 0.33µF, C REFP REFN COM values are ...

Page 8

Full-Duplex Analog Front-End ELECTRICAL CHARACTERISTICS (continued 3V 1.8V, internal reference (1.024V amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, V DAC output 0.33µF, C ...

Page 9

ELECTRICAL CHARACTERISTICS (continued 3V 1.8V, internal reference (1.024V amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, V DAC output 0.33µF, C REFP REFN COM values are ...

Page 10

Full-Duplex Analog Front-End ( 1.8V, internal reference (1.024V input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, V tial Tx DAC output REFP REFN COM ...

Page 11

OV = 1.8V, internal reference (1.024V input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, V tial Tx DAC output REFP REFN Rx ADC SIGNAL-TO-NOISE AND DISTORTION RATIO ...

Page 12

Full-Duplex Analog Front-End ( 1.8V, internal reference (1.024V input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, V tial Tx DAC output REFP REFN COM ...

Page 13

OV = 1.8V, internal reference (1.024V input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, V tial Tx DAC output REFP REFN Tx PATH CHANNEL-ID SPECTRAL PLOT WITH ...

Page 14

Full-Duplex Analog Front-End ( 1.8V, internal reference (1.024V input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, V tial Tx DAC output REFP REFN COM ...

Page 15

PIN NAME Positive Reference Voltage Input Terminal. Bypass with a 0.33µF capacitor to GND as close to REFP 1 REFP as possible 11, 39, Analog Supply Voltage. Bypass 41, 47 0.1µF capacitor. 3 ...

Page 16

Full-Duplex Analog Front-End The MAX19711 integrates three 12-bit auxiliary DACs (aux-DACs) and a 10-bit, 333ksps auxiliary ADC (aux- ADC) with 4:1 input multiplexer. The aux-DAC channels feature 1µs settling time for fast AGC, VGA, and AFC level setting. ...

Page 17

Table 1. Rx ADC Output Codes vs. Input Voltage DIFFERENTIAL INPUT DIFFERENTIAL INPUT (LSB) VOLTAGE V x 512/512 511 (+Full Scale - 1 LSB) REF V x 511/512 510 (+Full Scale - 2 LSB) REF V x 1/512 REF V ...

Page 18

Full-Duplex Analog Front-End CLK CLK t t DOQ DOI D0–D9 D0Q D1I D1Q Figure 3. Rx ADC System Timing Diagram Table 2. Tx Path Output Voltage vs. Input Codes (Internal Reference ...

Page 19

OCCUPIED AMPLITUDE CHANNEL 0dB -3dB -15dB -49.3dB -56dB (min) -57.1dB 0.63 1.3 CHANNEL EDGE f Figure 4. TD-SCDMA Filter Frequency Response Figure 6 shows the relationship among the clock, input data, and analog outputs. Channel ID data is latched on ...

Page 20

Full-Duplex Analog Front-End MAX19711 Tx DAC I-CH Tx DAC Q-CH FULL SCALE = 1.265V V = 1.06V COMD ZERO SCALE = 0.855V 0V Figure 5. Tx DAC Common-Mode DC Level at IDN, IDP or QDN, QDP Differential Outputs ...

Page 21

Table 3. MAX19711 Mode Control D11 D10 REGISTER NAME (MSB) 15 E11 = 0 E10 = 0 ENABLE-16 Reserved Reserved Aux-DAC1 1D11 1D10 Aux-DAC2 2D11 2D10 Aux-DAC3 3D11 3D10 IOFFSET — — QOFFSET — — COMSEL — — AD11 = ...

Page 22

Full-Duplex Analog Front-End Table 5. MAX19711 Tx, Rx, and FD Control Using SPI Commands ADDRESS DATA BITS 0000 (16-Bit Mode) and 1000 ...

Page 23

Table 6. MAX19711 Default (Power-On) Register Settings D11 D10 D9 REGISTER 16 NAME 15 (MSB) ENABLE- Aux Aux-DAC1 0 0 Aux-DAC2 0 0 Aux-DAC3 IOFFSET — — QOFFSET — — COMSEL — ...

Page 24

Full-Duplex Analog Front-End Table 10. Offset Control Bits for ID and QD Channels (IOFFSET or QOFFSET Mode) BITS IO5–IO0 WHEN IN IOFFSET MODE, BITS QO5–QO0 WHEN IN QOFFSET MODE IO5/QO5 IO4/QO4 • ...

Page 25

In FAST Rx mode, the Tx path (DAC core and Tx filter) is powered on. The Tx path outputs are set to midscale. In this mode, the Tx DAC input bus is disconnected from the DAC core and DA0–DA9 are ...

Page 26

Full-Duplex Analog Front-End sequence. SCLK can idle either high or low between tran- sitions. Figure 7 shows the detailed timing diagram of the 3-wire serial interface. Mode-Recovery Timing Figure 8 shows the mode-recovery timing diagram the ...

Page 27

If capacitive loading exceeds 5pF, then add a 10kΩ resistor in series with the output. Adding the series resistor helps drive larger load capacitance (< 15pF) at the expense of slower settling time. ...

Page 28

Full-Duplex Analog Front-End Table 18. Auxiliary ADC Data Output Mode AD10 SELECTION 0 Aux-ADC Data is Not Available on DOUT (Default) Aux-ADC Enters Data Output Mode Where 1 Data is Available on DOUT the system CLK frequency supplied ...

Page 29

SINGLE AUX-ADC CONVERSION WITH CONVERSION DATA READOUT AT A LATER TIME t CSD CS/WAKE 1 16 SCLK DIN DOUT AD10 = 0, AD0 = 1, PERFORM CONVERSION, DOUT DISABLED AUX-ADC REGISTER ADDRESS ...

Page 30

Full-Duplex Analog Front-End 25Ω 0.1μF 22pF V IN 0.33μF 0.1μF 25Ω 22pF 25Ω 0.1μF 22pF V IN 0.33μF 0.1μF 25Ω 22pF Figure 10. Balun Transformer-Coupled Single-Ended-to- Differential Input Drive for Rx ADC mode, even-order harmonics are lower as ...

Page 31

R1 600Ω R2 600Ω R3 600Ω Figure 13. Rx ADC DC-Coupled Differential Drive 70kΩ. If single-ended outputs are desired, use an amplifier to provide differential-to-single-ended conver- sion and select an amplifier with proper input common- mode voltage range. CDMA Application ...

Page 32

Full-Duplex Analog Front-End IAP IAN MAX2584 QAP ZIF RECEIVER AGC QAN IDP MAX2504 IDN DIRECT MODULATOR QDP VGA PA DETECT QDN PROGRAMMABLE OFFSET/GAIN/CM DAC1 TCXO DAC2 DAC3 ADC1 TEMPERATURE MEASURE ADC2 Figure 14. Typical Application Circuit for CDMA ...

Page 33

Dynamic Parameter Definitions ADC and DAC Static Parameter Definitions Integral Nonlinearity (INL) Integral nonlinearity is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best-straight-line fit or a ...

Page 34

Full-Duplex Analog Front-End In reality, there are other noise sources besides quanti- zation noise: thermal noise, reference noise, clock jitter, etc. SNR is computed by taking the ratio of the RMS signal to the RMS noise. RMS noise ...

Page 35

PART SAMPLING RATE (Msps) MAX19710 MAX19711 MAX19712 MAX19713 V = 2.7V TO 3.3V DD IAP IAN QAP QAN IDP CDMA FILTER IDN QDP CDMA FILTER QDN PROGRAMMABLE OFFSET/GAIN/CM DAC1 DAC2 DAC3 ADC1 ADC2 ...

Page 36

... Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 36 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2006 Maxim Integrated Products Springer ...

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