MAX19711ETN+T Maxim Integrated Products, MAX19711ETN+T Datasheet - Page 24

• Manufacturer Part Number: MAX19711ETN+T
• Description: IC ANLG FRNT END 56-TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX19711ETN+T

• Number Of Bits: 10
• Number Of Channels: 2
• Power (watts): 37.5mW
• Voltage - Supply, Analog: 3V
• Voltage - Supply, Digital: 3V
• Package / Case: 56-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10-Bit, 11Msps, Full-Duplex
Analog Front-End
Rx ADC outputs AD0–AD9 are forced to tri-state. The
Tx DAC DA0–DA9 inputs are internally pulled to OV
while the Tx DAC outputs are at 0V. The wake-up time
is 6.8µs to enter Rx mode, 5µs to enter Tx mode, and
6.8µs to enter FD mode. When the Rx ADC outputs
transition from tri-state to active, the last converted
word is placed on the digital output bus.
In standby mode, the reference is powered but all other
device functions are off. The wake-up time from stand-
by mode is 7.2µs to enter Rx mode, 21.8µs to enter Tx
mode, and 21.8µs to enter FD mode. When the Rx ADC
outputs transition from tri-state to active, the last con-
verted word is placed on the digital output bus.
Table 10. Offset Control Bits for ID and QD Channels (IOFFSET or QOFFSET Mode)
Note: For transmit full-scale select of ±410mV: 1 LSB = (820mV
(1V
24
Table 11. Common-Mode Select
(COMSEL Mode)
CM1
P-P
IO5/QO5
0
0
1
1
______________________________________________________________________________________
/ 1023) = 0.9775mV.
1
1
1
1
1
1
0
0
0
0
0
0
•
•
•
•
•
•
BITS IO5–IO0 WHEN IN IOFFSET MODE, BITS QO5–QO0 WHEN IN QOFFSET MODE
CM0
0
1
0
1
Tx PATH OUTPUT COMMON MODE (V)
IO4/QO4
1
1
1
0
0
0
0
0
0
1
1
1
•
•
•
•
•
•
1.36 (Default)
1.20
1.15
0.86
IO3/QO3
1
1
1
0
0
0
0
0
0
1
1
1
•
•
•
•
•
•
DD
IO2/QO2
P-P
,
1
1
1
0
0
0
0
0
0
1
1
1
•
•
•
•
•
•
/ 1023) = 0.8016mV. For transmit full scale select of ±500mV: 1 LSB =
The MAX19711 features FAST and SLOW modes for
switching between Rx and Tx operation. In FAST Tx
mode, the Rx ADC core is powered on but the ADC digi-
tal outputs AD0–AD9 are tri-stated. The Tx DAC digital
bus is active and the DAC core is fully operational.
Table 12. WAKEUP-SEL Register
W2
0
0
0
0
1
1
1
1
IO1/QO1
W1
0
0
1
1
0
0
1
1
1
1
0
1
0
0
0
0
1
0
1
1
•
•
•
•
•
•
W0
0
1
0
1
0
1
0
1
FAST and SLOW Rx and Tx Modes
Invalid Value. This value is ignored
POWER MODE AFTER WAKE-UP
when inadvertently written to the
IO0/QO0
1
0
1
0
1
0
0
1
0
1
0
1
•
•
•
•
•
•
WAKEUP-SEL register.
(WAKE-UP STATE)
SPI1-SLOW Rx
SPI2-SLOW Tx
SPI3-FAST Rx
SPI4-FAST Tx
FD (Default)
STBY
IDLE
OFFSET 1 LSB =
(VFS
0mV (Default)
-31 LSB
-30 LSB
-29 LSB
29 LSB
30 LSB
31 LSB
-2 LSB
-1 LSB
P-P
1 LSB
2 LSB
0mV
•
•
•
•
•
•
/ 1023)