MAX19711ETN+T Maxim Integrated Products, MAX19711ETN+T Datasheet - Page 7

• Manufacturer Part Number: MAX19711ETN+T
• Description: IC ANLG FRNT END 56-TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX19711ETN+T

• Number Of Bits: 10
• Number Of Channels: 2
• Power (watts): 37.5mW
• Voltage - Supply, Analog: 3V
• Voltage - Supply, Digital: 3V
• Package / Case: 56-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ELECTRICAL CHARACTERISTICS (continued)
(V
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, V
DAC output, C
values are at T
CS/WAKE High to DOUT Active
High
CS/WAKE High to DOUT Low
(Aux-ADC Conversion Time)
DOUT Low to CS/WAKE Setup
Time
SCLK Low to DOUT Data Out
CS/WAKE High to DOUT High
Impedance
CLK Rise to Q-DAC Data Hold
Time
CLK Duty Cycle
CLK Duty-Cycle Variation
Digital Output Rise/Fall Time
SERIAL-INTERFACE TIMING CHARACTERISTICS (Figures 7 and 9, Note 6)
Falling Edge of CS/WAKE to Rising
Edge of First SCLK Time
DIN to SCLK Setup Time
DIN to SCLK Hold Time
SCLK Pulse-Width High
SCLK Pulse-Width Low
SCLK Period
SCLK to CS/WAKE Setup Time
CS/WAKE High Pulse Width
MODE-RECOVERY TIMING CHARACTERISTICS (Figure 8)
Shutdown Wake-Up Time
DD
= 3V, OV
PARAMETER
A
REFP
DD
= +25°C.) (Note 1)
= 1.8V, internal reference (1.024V), C
= C
_______________________________________________________________________________________
REFN
= C
COM
= 0.33µF, C
SYMBOL
t
WAKE,SD
t
t
t
CONV
t
t
t
t
DHQ
CSW
t
t
CSD
DCS
t
CHZ
CSS
t
t
t
t
DH
CH
CD
DS
CL
CP
CS
L
< 5pF on all aux-DAC outputs, T
Figure 6 (Note 6)
20% to 80%
Bit AD0 set
Bit AD0 set, no averaging, f
CLK divider = 4
Bit AD0, AD10 set
Bit AD0, AD10 set
Bit AD0, AD10 set
From shutdown to Rx mode, ADC settles
to within 1dB SINAD
From shutdown to Tx mode, DAC settles to
within 10 LSB error
From aux-ADC enable to aux-ADC start
conversion
From shutdown to aux-DAC output valid
From shutdown to FD mode, ADC settles
to within 1dB SINAD, DAC settles to within
10 LSB error
L
≈ 10pF on all digital outputs, f
10-Bit, 11Msps, Full-Duplex
FS
= 410mV, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx
CONDITIONS
CLK
= 11MHz,
A
Analog Front-End
= T
CLK
MIN
= 11MHz (50% duty cycle), Rx ADC input
to T
MAX
MIN
10
10
25
25
50
10
80
0
0
, unless otherwise noted. Typical
TYP
±15
200
200
200
500
500
2.4
4.3
50
26
10
28
MAX
14.5
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
µs
%
%
7