MAX19711ETN+T Maxim Integrated Products, MAX19711ETN+T Datasheet - Page 3

• Manufacturer Part Number: MAX19711ETN+T
• Description: IC ANLG FRNT END 56-TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX19711ETN+T

• Number Of Bits: 10
• Number Of Channels: 2
• Power (watts): 37.5mW
• Voltage - Supply, Analog: 3V
• Voltage - Supply, Digital: 3V
• Package / Case: 56-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ELECTRICAL CHARACTERISTICS (continued)
(V
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, V
DAC output, C
values are at T
V
OV
Rx ADC DC ACCURACY
Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Gain Error
DC Gain Matching
Offset Matching
Gain Temperature Coefficient
Power-Supply Rejection
Rx ADC ANALOG INPUT
Input Differential Range
Input Common-Mode Voltage
Range
Input Impedance
DD
DD
DD
= 3V, OV
Supply Current
Supply Current
PARAMETER
A
REFP
DD
= +25°C.) (Note 1)
= 1.8V, internal reference (1.024V), C
= C
_______________________________________________________________________________________
REFN
= C
COM
= 0.33µF, C
SYMBOL
DNL
V
INL
C
V
R
CM
ID
IN
IN
L
< 5pF on all aux-DAC outputs, T
Idle mode: f
and at midscale, aux-ADC ON
Shutdown mode: CLK = 0 or OV
ADC OFF
FD m od e: f
b oth D AC channel s; f
AD C channel s; aux- D AC s O N and at
m i d scal e, aux- AD C O N
SPI1-Rx and SPI3-Rx modes: f
11MHz, f
channels; DAC input bus tri-stated; aux-
DACs ON and at midscale, aux-ADC ON
SPI2-Tx and SPI4-Tx modes: f
11MHz, f
channels; ADC output bus tri-stated; aux-
DACs ON and at midscale, aux-ADC ON
Standby mode: CLK = 0 or OV
DACs ON and at midscale, aux-ADC ON
Idle mode: f
and at midscale, aux-ADC ON
Shutdown mode: CLK = 0 or OV
ADC OFF
Residual DC offset error
Includes reference error
Offset (V
Gain (V
Differential or single-ended inputs
Switched capacitor load
L
≈ 10pF on all digital outputs, f
10-Bit, 11Msps, Full-Duplex
DD
DD
FS
IN
OUT
C LK
±5%)
= 1.87MHz on both ADC
= 410mV, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx
CLK
CLK
±5%)
= 620kHz on both DAC
CONDITIONS
= 11M H z, f
= 11MHz; aux-DACs ON
= 11MHz; aux-DACs ON
I N
= 1.87M H z on b oth
OU T
CLK
= 620kH z on
CLK
DD
A
DD
DD,
; aux-
Analog Front-End
= T
=
=
, aux-
CLK
aux-
MIN
= 11MHz (50% duty cycle), Rx ADC input
to T
MAX
-0.15
MIN
10
-5
-5
, unless otherwise noted. Typical
±0.512
V
±0.04
±0.08
±0.8
±0.5
±0.2
±0.9
±0.2
TYP
18.5
DD
±30
490
0.5
1.5
1.4
0.1
0.1
±9
80
5
/ 2
+0.15
MAX
+5
+5
7
5
ppm/°C
UNITS
%FS
%FS
LSB
LSB
LSB
LSB
Bits
mA
mA
µA
µA
dB
kΩ
pF
V
V
3