MAX19711ETN+T Maxim Integrated Products, MAX19711ETN+T Datasheet - Page 19

• Manufacturer Part Number: MAX19711ETN+T
• Description: IC ANLG FRNT END 56-TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX19711ETN+T

• Number Of Bits: 10
• Number Of Channels: 2
• Power (watts): 37.5mW
• Voltage - Supply, Analog: 3V
• Voltage - Supply, Digital: 3V
• Package / Case: 56-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 6 shows the relationship among the clock, input
data, and analog outputs. Channel ID data is latched on
the falling edge of the clock signal, and channel QD data
is latched on the rising edge of the clock signal, at which
point both ID and QD outputs are simultaneously updated.
The 3-wire serial interface controls the MAX19711 oper-
ation modes as well as the three 12-bit aux-DACs and
the 10-bit aux-ADC. Upon power-up, program the
MAX19711 to operate in the desired mode. Use the 3-
wire serial interface to program the device for shutdown,
idle, standby, FD, Rx, Tx, aux-DAC controls, or aux-ADC
conversion. A 16-bit data register sets the mode control
as shown in Table 3. The 16-bit word is composed of
four control bits (A3–A0) and 12 data bits (D11–D0).
Data is shifted in MSB first (D11) and LSB last (A0) for-
mat. Table 4 shows the MAX19711 power-management
modes. Table 5 shows the SPI-controlled Tx, Rx, and FD
modes. The serial interface remains active in all modes.
Program the control bits, A3–A0, in the register as shown
in Table 3 to select the operating mode. Modify A3–A0 bits
to select from ENABLE-16, Aux-DAC1, Aux-DAC2, Aux-
DAC3, IOFFSET, QOFFSET, COMSEL, Aux-ADC,
ENABLE-8, and WAKEUP-SEL modes. ENABLE-16 is the
default operating mode (see Table 6). This mode allows for
shutdown, idle, and standby states as well as switching
Figure 4. TD-SCDMA Filter Frequency Response
-56dB (min)
-49.3dB
-57.1dB
-15dB
-3dB
0dB
AMPLITUDE
______________________________________________________________________________________
CHANNEL EDGE
3-Wire Serial Interface and
0.63
OCCUPIED
CHANNEL
SPI Register Description
1.3
f
Operation Modes
C
Tx DAC Timing
FILTER RESPONSE
10-Bit, 11Msps, Full-Duplex
CDMA
between FAST, SLOW, Rx and Tx modes. Tables 4 and 5
show the required SPI settings for each mode.
In ENABLE-16 mode, the aux-DACs have independent
control bits E4, E5, and E6, bit E7 sets the Tx path full-
scale outputs, and bit E9 enables the aux-ADC. Table 7
shows the auxiliary DAC enable codes. Table 8 shows
the full-scale output selection. Table 9 shows the auxil-
iary ADC enable code. Bits E11 and E10 are reserved.
Program bits E11 and E10 to logic-low. Bits E3 and E8
are not used.
Modes Aux-DAC1, Aux-DAC2, and Aux-DAC3 select
the aux-DAC channels named DAC1, DAC2, and DAC3
and hold the data inputs for each DAC. Bits _D11–_D0
are the data inputs for each aux-DAC and can be pro-
grammed through SPI. The MAX19711 also includes
two 6-bit registers that can be programmed to adjust the
offsets for the Tx path ID and QD channels indepen-
dently (see Table 10). Use the COMSEL mode to select
the output common-mode voltage with bits CM1 and
CM0 (see Table 11). Use Aux-ADC mode to start the
auxiliary ADC conversion (see the 10-Bit, 333ksps
Auxiliary ADC section for details). Use ENABLE-8 mode
for faster enable and switching between shutdown, idle,
and standby states as well as switching between FAST,
SLOW, Rx and Tx modes and the FD mode.
The WAKEUP-SEL register selects the operating mode
that the MAX19711 is to enter immediately after coming
out of shutdown (Table 12). See the Wake-Up Function
section for more information.
DAC sin(x)/x
RESPONSE
Analog Front-End
4.285
f
IMAGE
4.915
f
CLK
Tx PATH:
SFDR = 75dBc
THD = -75dBc
SNR = 55.9dB
NOT TO SCALE
FREQ (MHz)
19