IDT82V3288BCG IDT, Integrated Device Technology Inc, IDT82V3288BCG Datasheet - Page 71

• Manufacturer Part Number: IDT82V3288BCG
• Description: IC PLL WAN 3E STRATUM 2 208CABGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of IDT82V3288BCG

• Input: CMOS, LVDS, PECL, TTL
• Output: CMOS, LVDS, PECL, TTL
• Frequency - Max: 622.08MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 208-CABGA
• Frequency-max: 622.08MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V3288BCG

INPUT_MODE_CNFG - Input Mode Configuration
Programming Information
IDT82V3288
Address: 09H
Type: Read / Write
Default Value: 10100XX0
AUTO_EXT_SY
4 - 3
Bit
7
6
5
2
1
0
NC_EN
7
AUTO_EXT_SYNC_EN
PH_ALARM_TIMEOUT
REVERTIVE_MODE
SYNC_FREQ[1:0]
MASTER_SLAVE
IN_SONET_SDH
EXT_SYNC_EN
EXT_SYNC_EN
Name
6
This bit is valid only when the SYNC_BYPASS bit (b7, 7CH) is ‘0’.
Refer to the description of the EXT_SYNC_EN bit (b6, 09H).
This bit is valid only when the SYNC_BYPASS bit (b7, 7CH) is ‘0’.
This bit, together with the AUTO_EXT_SYNC_EN bit (b7, 09H), determines whether the selected frame sync input signal is
enabled to synchronize the frame sync output signals.
This bit determines how to clear the phase lock alarm.
0: The phase lock alarm will be cleared when a ‘1’ is written to the corresponding INn_PH_LOCK_ALARM bit (b4/0,
43H~49H).
1: The phase lock alarm will be cleared after a period ( = TIME_OUT_VALUE[5:0] (b5~0, 08H) X MULTI_FACTOR[1:0]
(b7~6, 08H) in second ) which starts from when the alarm is raised. (default)
These bits set the frequency of the frame sync signals input on the EX_SYNC1 ~ EX_SYNC3 pins.
00: 8 kHz (default)
01: 8 kHz.
10: 4 kHz.
11: 2 kHz.
This bit selects the SDH or SONET network type.
0: SDH. The DPLL required clock is 2.048 MHz when the IN_FREQ[3:0] bits (b3~0, 14H~17H & 19H~22H) are ‘0001’; the
T0/T4 DPLL output from the 16E1/16T1 path is 16E1; and OUT9 outputs a 2.048 MHz signal if enabled.
1: SONET. The DPLL required clock is 1.544 MHz when the IN_FREQ[3:0] bits (b3~0, 14H~17H & 19H~22H) are ‘0001’; the
T0/T4 DPLL output from the 16E1/16T1 path is 16T1; and OUT9 outputs a 1.544 MHz signal if enabled.
The default value of this bit is determined by the SONET/ SDH pin during reset.
This bit is read only. It indicates the value of the MS/ SL pin.
This bit selects Revertive or Non-Revertive switch for T0 path.
0: Non-Revertive switch. (default)
1: Revertive switch.
Its default value is determined by the MS/ SL pin during reset.
AUTO_EXT_SYNC_EN
PH_ALARM_TI
MEOUT
don’t-care
5
0
1
SYNC_FREQ1
EXT_SYNC_EN
4
0
1
1
71
SYNC_FREQ0
3
Enabled if the T0 selected input clock is IN11; otherwise, disabled.
Description
IN_SONET_SD
H
2
Synchronization
Disabled (default)
Enabled
MASTER_SLAV
E
1
March 14, 2007
REVERTIVE_M
ODE
WAN PLL
0