IDT82V3288BCG IDT, Integrated Device Technology Inc, IDT82V3288BCG Datasheet - Page 110

• Manufacturer Part Number: IDT82V3288BCG
• Description: IC PLL WAN 3E STRATUM 2 208CABGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of IDT82V3288BCG

• Input: CMOS, LVDS, PECL, TTL
• Output: CMOS, LVDS, PECL, TTL
• Frequency - Max: 622.08MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 208-CABGA
• Frequency-max: 622.08MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V3288BCG

DECAY_RATE_3_CNFG - Decay Rate for Leaky Bucket Configuration 3
IN_FREQ_READ_CH_CNFG - Input Clock Frequency Read Channel Selection
Programming Information
IDT82V3288
Address: 40H
Type: Read / Write
Default Value: XXXXXX01
Address: 41H
Type: Read / Write
Default Value: XXXX0000
7 - 2
1 - 0
Bit
7 - 4
3 - 0
Bit
7
-
7
-
DECAY_RATE_3_DATA[1:0]
IN_FREQ_READ_CH[3:0]
Name
Name
6
-
-
-
6
-
Reserved.
These bits select an input clock, the frequency of which with respect to the reference clock can be read.
0000: Reserved. (default)
0001: IN1.
0010: IN2.
......
1101: IN13.
1110: IN14.
1111: Reserved.
Reserved.
These bits set a decay rate for the internal leaky bucket accumulator:
00: The accumulator decreases by 1 in every 128 ms with no event detected.
01: The accumulator decreases by 1 in every 256 ms with no event detected. (default)
10: The accumulator decreases by 1 in every 512 ms with no event detected.
11: The accumulator decreases by 1 in every 1024 ms with no event detected.
5
-
5
-
4
-
4
-
IN_FREQ_READ
110
_CH3
3
3
-
Description
Description
IN_FREQ_READ
_CH2
2
2
-
IN_FREQ_READ
DECAY_RATE_
_CH1
3_DATA1
1
1
IN_FREQ_READ
DECAY_RATE_
March 14, 2007
3_DATA0
_CH0
0
0
WAN PLL