IDT82V3288BCG IDT, Integrated Device Technology Inc, IDT82V3288BCG Datasheet - Page 6

• Manufacturer Part Number: IDT82V3288BCG
• Description: IC PLL WAN 3E STRATUM 2 208CABGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of IDT82V3288BCG

• Input: CMOS, LVDS, PECL, TTL
• Output: CMOS, LVDS, PECL, TTL
• Frequency - Max: 622.08MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 208-CABGA
• Frequency-max: 622.08MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V3288BCG

List of Tables
Table 1: Pin Description ............................................................................................................................................................................................. 13
Table 2: Related Bit / Register in Chapter 3.2 ........................................................................................................................................................... 20
Table 3: Related Bit / Register in Chapter 3.3 ........................................................................................................................................................... 21
Table 4: Related Bit / Register in Chapter 3.4 ........................................................................................................................................................... 23
Table 5: Related Bit / Register in Chapter 3.5 ........................................................................................................................................................... 25
Table 6: Input Clock Selection for T0 Path ................................................................................................................................................................ 26
Table 7: Input Clock Selection for T4 Path ................................................................................................................................................................ 26
Table 8: External Fast Selection ................................................................................................................................................................................ 26
Table 9: Related Bit / Register in Chapter 3.6 ........................................................................................................................................................... 27
Table 10: Coarse Phase Limit Programming (the selected input clock of 2 kHz, 4 kHz or 8 kHz) .............................................................................. 28
Table 11: Coarse Phase Limit Programming (the selected input clock of other than 2 kHz, 4 kHz and 8 kHz) .......................................................... 28
Table 12: Related Bit / Register in Chapter 3.7 ........................................................................................................................................................... 29
Table 13: Conditions of Qualified Input Clocks Available for T0 & T4 Selection ......................................................................................................... 30
Table 14: Related Bit / Register in Chapter 3.8 ........................................................................................................................................................... 31
Table 15: T0 DPLL Operating Mode Control ............................................................................................................................................................... 32
Table 16: T4 DPLL Operating Mode Control ............................................................................................................................................................... 34
Table 17: Related Bit / Register in Chapter 3.9 ........................................................................................................................................................... 34
Table 18: Frequency Offset Control in Temp-Holdover Mode ..................................................................................................................................... 35
Table 19: Frequency Offset Control in Holdover Mode ............................................................................................................................................... 36
Table 20: Holdover Frequency Offset Read ................................................................................................................................................................ 36
Table 21: Related Bit / Register in Chapter 3.10 ......................................................................................................................................................... 37
Table 22: Related Bit / Register in Chapter 3.11 ......................................................................................................................................................... 39
Table 23: Related Bit / Register in Chapter 3.12 ......................................................................................................................................................... 40
Table 24: Outputs on OUT1 ~ OUT7 if Derived from T0/T4 DPLL Outputs ................................................................................................................ 41
Table 25: Outputs on OUT1 ~ OUT7 if Derived from T0/T4 APLL .............................................................................................................................. 42
Table 26: Outputs on OUT8 & OUT9 ........................................................................................................................................................................... 42
Table 27: Frame Sync Input Signal Selection .............................................................................................................................................................. 43
Table 28: Synchronization Control ............................................................................................................................................................................... 43
Table 29: Related Bit / Register in Chapter 3.13 ......................................................................................................................................................... 44
Table 30: Device Master / Slave Control ..................................................................................................................................................................... 45
Table 31: Related Bit / Register in Chapter 3.15 ......................................................................................................................................................... 46
Table 32: Microprocessor Interface ............................................................................................................................................................................. 50
Table 33: Access Timing Characteristics in EPROM Mode ......................................................................................................................................... 51
Table 34: Read Timing Characteristics in Multiplexed Mode ....................................................................................................................................... 52
Table 35: Write Timing Characteristics in Multiplexed Mode ....................................................................................................................................... 53
Table 36: Read Timing Characteristics in Intel Mode .................................................................................................................................................. 54
Table 37: Write Timing Characteristics in Intel Mode .................................................................................................................................................. 55
Table 38: Read Timing Characteristics in Motorola Mode ........................................................................................................................................... 56
Table 39: Write Timing Characteristics in Motorola Mode ........................................................................................................................................... 57
Table 40: Read Timing Characteristics in Serial Mode ................................................................................................................................................ 58
Table 41: Write Timing Characteristics in Serial Mode ................................................................................................................................................ 59
Table 42: JTAG Timing Characteristics ....................................................................................................................................................................... 60
Table 43: Register List and Map .................................................................................................................................................................................. 61
Table 44: Power Consumption and Maximum Junction Temperature ....................................................................................................................... 152
Table 45: Thermal Data ............................................................................................................................................................................................. 152
Table 46: Absolute Maximum Rating ......................................................................................................................................................................... 153
Table 47: Recommended Operation Conditions ........................................................................................................................................................ 153
Table 48: AMI Input / Output Port Electrical Characteristics ...................................................................................................................................... 155
List of Tables
6
March 14, 2007