IDT82V3288BCG IDT, Integrated Device Technology Inc, IDT82V3288BCG Datasheet - Page 150

• Manufacturer Part Number: IDT82V3288BCG
• Description: IC PLL WAN 3E STRATUM 2 208CABGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of IDT82V3288BCG

• Input: CMOS, LVDS, PECL, TTL
• Output: CMOS, LVDS, PECL, TTL
• Frequency - Max: 622.08MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 208-CABGA
• Frequency-max: 622.08MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V3288BCG

7.2.10
SYNC_MONITOR_CNFG - Sync Monitor Configuration
Programming Information
IDT82V3288
Address:7CH
Type: Read / Write
Default Value: 00101011
SYNC_BYPASS
6 - 4
3 - 0
Bit
7
7
SYNCHRONIZATION CONFIGURATION REGISTERS
SYNC_MON_LIMT[2:0]
SYNC_BYPASS
SYNC_MON_LIMT2
Name
-
6
This bit selects one frame sync input signal to synchronize the frame sync output signals.
0: EX_SYNC1 is selected. (default)
1: When the T0 selected input clock is any of IN1 ~ IN3, IN5, IN7, IN8, IN10 ~ IN14, EX_SYNC1 is selected; when the T0
selected input clock is IN4 or IN6, EX_SYNC2 is selected; when the T0 selected input clock is IN9, EX_SYNC3 is selected;
when there is no T0 selected input clock, no frame sync input signal is selected.
These bits set the limit for the external sync alarm.
000: ±1 UI.
001: ±2 UI.
010: ±3 UI. (default)
011: ±4 UI.
100: ±5 UI.
101: ±6 UI.
110: ±7 UI.
111: ±8 UI.
These bits must be set to ‘1011’.
SYNC_MON_LIMT1
5
SYNC_MON_LIMT0
150
4
Description
3
-
2
-
1
-
March 14, 2007
WAN PLL
0
-