ADF4153BRUZ Analog Devices Inc, ADF4153BRUZ Datasheet - Page 9

• Manufacturer Part Number: ADF4153BRUZ
• Description: IC SYNTH PLL RF F-N FREQ 16TSSOP
• Manufacturer: Analog Devices Inc
• Type: Fractional N Synthesizer (RF)r

Specifications of ADF4153BRUZ

• Pll: Yes
• Input: CMOS
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:1
• Differential - Input:output: Yes/No
• Frequency - Max: 4GHz
• Divider/multiplier: No/Yes
• Voltage - Supply: 2.7 V ~ 3.3 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Frequency-max: 4GHz
• Pll Type: Frequency Synthesis
• Frequency: 4GHz
• Supply Current: 20mA
• Supply Voltage Range: 2.7V To 3.3V
• Digital Ic Case Style: TSSOP
• No. Of Pins: 16
• Operating Temperature Range: -40°C To +85°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADF4153EBZ1 - BOARD EVAL FOR ADF4153
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION
The reference input stage is shown in Figure 11. SW1 and SW2
are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed and SW1 and SW2 are
opened. This ensures that there is no loading of the REF
on power-down.
RF INPUT STAGE
The RF input stage is shown in Figure 12. It is followed by a
2-stage limiting amplifier to generate the current-mode logic
(CML) clock levels needed for the prescaler.
RF
RF
IN
IN
A
B
REF
IN
GENERATOR
NC
POWER-DOWN
Figure 11. Reference Input Stage
SW1
CONTROL
BIAS
Figure 12. RF Input Stage
NO
NC
SW3
SW2
2kΩ
100kΩ
1.6V
BUFFER
2kΩ
TO R COUNTER
AGND
AV
DD
IN
pin
Rev. D | Page 9 of 24
RF INT DIVIDER
The RF INT CMOS counter allows a division ratio in the PLL
feedback counter. Division ratios from 31 to 511 are allowed.
INT, FRAC, MOD, AND R RELATIONSHIP
The INT, FRAC, and MOD values, in conjunction with the
R counter, make it possible to generate output frequencies that
are spaced by fractions of the phase frequency detector (PFD).
See the RF Synthesizer: A Worked Example section for more
information. The RF VCO frequency (RF
where:
RF
oscillator (VCO).
INT is the preset divide ratio of the binary 9-bit counter (31
to 511).
MOD is the preset fractional modulus (2 to 4095).
FRAC is the numerator of the fractional division (0 to MOD − 1).
The PFD frequency is given by:
where:
REF
D is the REF
R is the preset divide ratio of the binary 4-bit programmable
reference counter (1 to 15).
RF R COUNTER
The 4-bit RF R counter allows the input reference frequency
(REF
the PFD. Division ratios from 1 to 15 are allowed.
OUT
INPUT STAGE
IN
RF
F
IN
FROM RF
PFD
is the output frequency of the external voltage controlled
is the reference input frequency.
) to be divided down to produce the reference clock to
OUT
= REF
= F
IN
PFD
doubler bit.
IN
RF N DIVIDER
× (INT + (FRAC/MOD))
× (1 + D)/R
N-COUNTER
REG
INT
Figure 13. RF N Divider
MOD
REG
N = INT + FRAC/MOD
INTERPOLATOR
THIRD-ORDER
FRACTIONAL
OUT
) equation is
VALUE
FRAC
ADF4153
TO PFD
(1)
(2)