ADF4153BRUZ Analog Devices Inc, ADF4153BRUZ Datasheet
ADF4153BRUZ
Specifications of ADF4153BRUZ
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ADF4153BRUZ Summary of contents
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FEATURES RF bandwidth to 4 GHz 2 3.3 V power supply Separate V allows extended tuning voltage P Y version available: −40°C to +125°C Programmable fractional modulus Programmable charge pump currents 3-wire serial interface Analog and digital lock ...
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ADF4153 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 4 Timing Specifications .................................................................. 5 Absolute Maximum Ratings............................................................ 6 ESD Caution.................................................................................. 6 Pin Configurations and Function Descriptions ...
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Rev. A Renumbered Figures and Tables ...................................... Universal Changes to Specifications.................................................................3 Changes to Pin Function Description ............................................7 Changes to RF Power-Down Section............................................17 Changes to PCB Design Guidelines for Chip Scale Package Section ...............................................................................21 Updated Outline Dimensions........................................................22 Updated ...
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ADF4153 SPECIFICATIONS SDV = 2 3 dBm referred to 50 Ω. Table 1. Parameter B Version RF CHARACTERISTICS ( Input Frequency (RF ) 0.5/4.0 IN 0.5/4.0 1.0/4.0 ...
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Parameter B Version NOISE CHARACTERISTICS Normalized Phase Noise Floor −220 5 (PN ) SYNTH Normalized 1/f Noise ( −114 1_f 7 Phase Noise Performance 8 1750 MHz Output −102 1 Operating temperature for B version is −40°C to ...
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ADF4153 ABSOLUTE MAXIMUM RATINGS T = 25°C, GND = AGND = DGND = SDV , unless otherwise noted Table 3. Parameter V to GND ...
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PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS SET CPGND 3 14 ADF4153 AGND 4 13 TOP VIEW (Not to Scale REF 8 ...
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ADF4153 TYPICAL PERFORMANCE CHARACTERISTICS Loop bandwidth = 20 kHz, reference = 250 MHz, VCO = Sirenza 1750T VCO, evaluation board = EVAL-ADF4153EBZ1, measurements taken on the Agilent E5500 phase noise system. –30 20kHz LOOP BW, LOWEST NOISE MODE –40 RF ...
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CIRCUIT DESCRIPTION REFERENCE INPUT SECTION The reference input stage is shown in Figure 11. SW1 and SW2 are normally closed switches. SW3 is normally open. When power-down is initiated, SW3 is closed and SW1 and SW2 are opened. This ensures ...
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ADF4153 PHASE FREQUENCY DETECTOR (PFD) AND CHARGE PUMP The PFD takes inputs from the R counter and N counter and produces an output proportional to the phase and frequency difference between them. Figure simplified schematic of the ...
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Table 6. Register Summary 9-BIT INTEGER VALUE (INT) DB23 DB22 DB21 DB20 DB19 DB18 DB17 FL1 MUXOUT DB23 DB22 DB21 DB20 DB19 DB18 DB17 12-BIT FRACTIONAL VALUE ...
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ADF4153 Table 7. N Divider Register Map (R0) 9-BIT INTEGER VALUE (INT) DB23 DB22 DB21 DB20 DB19 DB18 DB17 N8 N7 FL1 ...
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Table 8. R Divider Register Map (R1) MUXOUT DB23 DB22 DB21 DB18 DB20 DB19 LOAD CONTROL P1 PRESCALER 0 NORMAL OPERATION 0 4/5 1 LOAD RESYNC 1 8 MUXOUT 0 ...
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ADF4153 Table 9. Control Register Map (R2) RESYNC DB15 DB14 DB13 ...
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Table 10. Noise and Spur Register (R3) DB10 0 DB9, DB8, DB7, DB6, DB2 00000 11100 11111 NOISE AND SPUR RESERVED MODE DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB10, DB5, DB4, DB3 ...
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ADF4153 N DIVIDER REGISTER, R0 With R0[1, 0] set to [0, 0], the on-chip N divider register is programmed. Table 7 shows the input data format for programming this register. 9-Bit INT Value These nine bits control what is loaded ...
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When a power-down is activated, the following events occur: 1. All active dc current paths are removed. 2. The synthesizer counters are forced to their load state conditions. 3. The charge pump is forced into three-state mode. 4. The digital ...
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ADF4153 INITIALIZATION SEQUENCE The following initialization sequence should be followed upon powering up the part: 1. Write all zeros to the noise and spur register. This ensures that all test modes are cleared. 2. Write again to the noise and ...
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The programmable modulus is also very useful for multi- standard applications dual-mode phone requires PDC and GSM 1800 standards, the programmable modulus is of great benefit. PDC requires 25 kHz channel step resolution, whereas GSM 1800 requires 200 ...
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ADF4153 Reference Spurs Reference spurs are generally not a problem in fractional-N synthesizers because the reference offset is far outside the loop bandwidth. However, any reference feedthrough mechan- ism that bypasses the loop can cause a problem. One such mechanism ...
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When operating in this mode, the maximum SCLOCK rate of the ADuC812 is 4 MHz. This means that the maximum rate at which the output frequency can be changed is 180 kHz. ADSP-21xx Interface Figure 19 shows the interface between ...
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ADF4153 APPLICATIONS INFORMATION LOCAL OSCILLATOR FOR A GSM BASE STATION TRANSMITTER Figure 20 shows the ADF4153 being used with a VCO to produce the local oscillator (LO) for a GSM base station transmitter. The reference input signal is applied to ...
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OUTLINE DIMENSIONS 0.15 0.05 PIN 1 INDICATOR 12° MAX 1.00 0.85 0.80 SEATING PLANE 5.10 5.00 4. 4.50 6.40 4.40 BSC 4. PIN 1 1.20 MAX 0.20 0.09 0.30 0.65 0.19 SEATING BSC PLANE COPLANARITY 0.10 ...
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... ADF4153BRU −40°C to +85°C ADF4153BRU-REEL7 −40°C to +85°C ADF4153BRUZ −40°C to +85°C ADF4153BRUZ-RL −40°C to +85°C ADF4153BRUZ-RL7 −40°C to +85°C ADF4153YRUZ −40°C to +125°C ADF4153YRUZ-RL −40°C to +125°C ADF4153YRUZ-RL7 −40°C to +125°C ADF4153BCP − ...