ADF4153BRUZ Analog Devices Inc, ADF4153BRUZ Datasheet - Page 5

• Manufacturer Part Number: ADF4153BRUZ
• Description: IC SYNTH PLL RF F-N FREQ 16TSSOP
• Manufacturer: Analog Devices Inc
• Type: Fractional N Synthesizer (RF)r

Specifications of ADF4153BRUZ

• Pll: Yes
• Input: CMOS
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:1
• Differential - Input:output: Yes/No
• Frequency - Max: 4GHz
• Divider/multiplier: No/Yes
• Voltage - Supply: 2.7 V ~ 3.3 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Frequency-max: 4GHz
• Pll Type: Frequency Synthesis
• Frequency: 4GHz
• Supply Current: 20mA
• Supply Voltage Range: 2.7V To 3.3V
• Digital Ic Case Style: TSSOP
• No. Of Pins: 16
• Operating Temperature Range: -40°C To +85°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADF4153EBZ1 - BOARD EVAL FOR ADF4153
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Parameter
NOISE CHARACTERISTICS
1
2
3
4
5
6
7
8
TIMING SPECIFICATIONS
AV
dBm referred to 50 Ω.
Table 2.
Parameter
t
t
t
t
t
t
t
1
2
3
4
5
6
7
Operating temperature for B version is −40°C to +85°C.
Operating temperature for Y version is −40°C to +125°C.
AC coupling ensures AV
Guaranteed by design. Sample tested to ensure compliance.
The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log(N) (where N is the N divider
value) and 10 log(F
The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency, F
and at an offset frequency, f, is given by PN = P
The phase noise is measured with the EVAL-ADF4153EBZ1 and the Agilent E5500 phase noise system.
f
REFIN
Normalized Phase Noise Floor
Normalized 1/f Noise (PN
Phase Noise Performance
1750 MHz Output
DD
(PN
= 100 MHz; F
= DV
SYNTH
DD
)
5
= SDV
DATA
PFD
CLK
PFD
LE
LE
= 25 MHz; offset frequency = 5 kHz; RF
). PN
8
DD
DD
Limit at T
20
10
10
25
25
10
20
/2 bias.
SYNTH
= 2.7 V to 3.3 V; V
DB23 (MSB)
t
= PN
1
1_f
7
)
6
TOT
MIN
− 10 log(F
to T
B Version
−220
−114
−102
MAX
1_f
PFD
t
+ 10 log(10 kHz/f) + 20 log(F
2
P
(B Version)
) − 20 log(N).
= AV
DB22
1
DD
OUT
t
Y Version
−220
−114
−102
3
to 5.5 V; AGND = DGND = 0 V; T
= 1750 MHz; N = 70; loop BW = 20 kHz; lowest noise mode.
Figure 2. Timing Diagram
Rev. D | Page 5 of 24
2
DB2
RF
Unit
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in ADIsimPLL.
t
4
t
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
5
(CONTROL BIT C2)
Test Conditions/Comments
PLL loop BW = 500 kHz
Measured at 10 kHz offset, normalized to 1 GHz
@ VCO output
@ 5 kHz offset, 25 MHz PFD frequency
DB1
A
= T
MIN
Test Conditions/Comments
LE setup time
DATA to CLK setup time
DATA to CLK hold time
CLK high duration
CLK low duration
CLK to LE setup time
LE pulse width
to T
MAX
t
6
(CONTROL BIT C1)
, unless otherwise noted;
DB0 (LSB)
t
7
ADF4153
RF
,