ADF4153BRUZ Analog Devices Inc, ADF4153BRUZ Datasheet - Page 17

• Manufacturer Part Number: ADF4153BRUZ
• Description: IC SYNTH PLL RF F-N FREQ 16TSSOP
• Manufacturer: Analog Devices Inc
• Type: Fractional N Synthesizer (RF)r

Specifications of ADF4153BRUZ

• Pll: Yes
• Input: CMOS
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:1
• Differential - Input:output: Yes/No
• Frequency - Max: 4GHz
• Divider/multiplier: No/Yes
• Voltage - Supply: 2.7 V ~ 3.3 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Frequency-max: 4GHz
• Pll Type: Frequency Synthesis
• Frequency: 4GHz
• Supply Current: 20mA
• Supply Voltage Range: 2.7V To 3.3V
• Digital Ic Case Style: TSSOP
• No. Of Pins: 16
• Operating Temperature Range: -40°C To +85°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADF4153EBZ1 - BOARD EVAL FOR ADF4153
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

When a power-down is activated, the following events occur:
1.
2.
3.
4.
5.
6.
Lock Detect Precision (LDP)
When DB5 is programmed to 0, 24 consecutive PFD cycles of
15 ns must occur before digital lock detect is set. When this bit
is programmed to 1, 40 consecutive reference cycles of 15 ns
must occur before digital lock detect is set.
Phase Detector Polarity
DB6 in the ADF4153 sets the phase detector polarity. When the
VCO characteristics are positive, this should be set to 1. When
they are negative, it should be set to 0.
Charge Pump Current Setting
DB7, DB8, DB9, and DB10 set the charge pump current setting.
This should be set to the charge pump current that the loop
filter is designed with (see Table 9).
REF
Setting DB11 to 0 feeds the REF
R counter, disabling the doubler. Setting this bit to 1 multiplies
the REF
R counter. When the doubler is disabled, the REF
is the active edge at the PFD input to the fractional synthesizer.
When the doubler is enabled, both the rising and falling edges
of REF
When the doubler is enabled and the lowest spur mode is chosen,
the in-band phase noise performance is sensitive to the REF
duty cycle. The phase noise degradation can be as much as 5 dB
for the REF
noise is insensitive to the REF
mode and in the lowest noise and spur mode. The phase noise
is insensitive to REF
The maximum allowed REF
enabled is 30 MHz.
IN
All active dc current paths are removed.
The synthesizer counters are forced to their load state
conditions.
The charge pump is forced into three-state mode.
The digital lock detect circuitry is reset.
The RF
The input register remains active and capable of loading
and latching data.
Doubler
IN
IN
become active edges at the PFD input.
frequency by a factor of 2 before feeding into the 4-bit
IN
IN
duty cycles outside a 45% to 55% range. The phase
input is debiased.
IN
duty cycle when the doubler is disabled.
IN
IN
frequency when the doubler is
IN
duty cycle in the lowest noise
signal directly to the 4-bit RF
IN
falling edge
IN
Rev. D | Page 17 of 24
NOISE AND SPUR REGISTER, R3
With R3[1, 0] set to [1, 1], the on-chip noise and spur register
is programmed. Table 10 shows the input data format for
programming this register.
Noise and Spur Mode
Noise and spur mode allows the user to optimize a design either
for improved spurious performance or for improved phase
noise performance. When the low spur setting is chosen, dither
is enabled. This randomizes the fractional quantization noise so
that it resembles white noise rather than spurious noise. As a
result, the part is optimized for improved spurious
performance. This operation would normally be used when the
PLL closed-loop bandwidth is wide, for fast-locking applica-
tions. (Wide-loop bandwidth is seen as a loop bandwidth
greater than 1/10 of the RF
wide-loop filter does not attenuate the spurs to the same level as
a narrow-loop bandwidth.
When the low noise and spur setting is enabled, dither is
disabled. This optimizes the synthesizer to operate with
improved noise performance. However, the spurious
performance is degraded in this mode compared to the low
spur setting.
To further improve noise performance, the lowest noise setting
option can be used, which reduces the phase noise. As well as
disabling the dither, it also ensures that the charge pump is
operating in an optimum region for noise performance. This
setting is extremely useful where a narrow-loop filter band-
width is available. The synthesizer ensures extremely low noise
and the filter attenuates the spurs. The typical performance
characteristics give the user an idea of the trade-off in a typical
W-CDMA setup for the different noise and spur settings.
RESERVED BITS
These bits should be set to 0 for normal operation.
OUT
channel step resolution (f
ADF4153
RES
).) A