ADF4153BRUZ Analog Devices Inc, ADF4153BRUZ Datasheet - Page 22

• Manufacturer Part Number: ADF4153BRUZ
• Description: IC SYNTH PLL RF F-N FREQ 16TSSOP
• Manufacturer: Analog Devices Inc
• Type: Fractional N Synthesizer (RF)r

Specifications of ADF4153BRUZ

• Pll: Yes
• Input: CMOS
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:1
• Differential - Input:output: Yes/No
• Frequency - Max: 4GHz
• Divider/multiplier: No/Yes
• Voltage - Supply: 2.7 V ~ 3.3 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Frequency-max: 4GHz
• Pll Type: Frequency Synthesis
• Frequency: 4GHz
• Supply Current: 20mA
• Supply Voltage Range: 2.7V To 3.3V
• Digital Ic Case Style: TSSOP
• No. Of Pins: 16
• Operating Temperature Range: -40°C To +85°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADF4153EBZ1 - BOARD EVAL FOR ADF4153
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADF4153
APPLICATIONS INFORMATION
LOCAL OSCILLATOR FOR A GSM BASE STATION
TRANSMITTER
Figure 20 shows the ADF4153 being used with a VCO to
produce the local oscillator (LO) for a GSM base station
transmitter.
The reference input signal is applied to the circuit at REF
in this case, is terminated in 50 Ω. A 25 MHz reference is used,
which is fed directly to the PFD. To achieve 200 kHz channel
spacing, a modulus of 125 is necessary. Note that with a modulus
of 125, which is not divisible by 2, 3 or 6, subfractional spurs are
avoided. See the Spur Mechanisms section for more information.
The charge pump output of the ADF4153 drives the loop filter.
FREF
IN
1000pF
10µF
51Ω
5.1kΩ
1000pF
10
100nF
8
SV
REF
R
CLK
DATA
LE
Figure 20. Local Oscillator for a GSM Base Station Transmitter
SET
DD
AV
3
7
IN
V
ADF4153
DD
DD
4
15
DV
9
MUXOUT
DD
RF
RF
16
IN
IN
IN
V
CP
and,
V
A
P
B
P
100nF
2
14
6
5
Rev. D | Page 22 of 24
100pF
100pF
LOCK
DETECT
22nF
10µF
DECOUPLING CAPACITORS SHOULD BE PLACED
AS CLOSE AS POSSIBLE TO THE PINS.
51Ω
The charge pump current is I
calculate the loop filter. It is designed for a loop bandwidth of
20 kHz and a phase margin of 45 degrees.
The loop filter output drives the VCO, which in turn is fed back
to the RF input of the PLL synthesizer. It also drives the RF output
terminal. A T-circuit configuration provides 50 Ω matching
between the VCO output, the RF output, and the RF
of the synthesizer.
In a PLL system, it is important to know when the loop is in
lock. This is achieved by using the MUXOUT signal from the
synthesizer. The MUXOUT pin can be programmed to monitor
various internal signals in the synthesizer. One of these is the
lock detect signal.
82Ω
270nF
160Ω
8.2nF
2
VCO190-902T
V
CC
14
10pF
CP
10
= 5 mA. ADIsimPLL is used to
100nF
100pF
100pF
18Ω
RF
OUT
18Ω
18Ω
IN
terminal