ADF4153BRUZ Analog Devices Inc, ADF4153BRUZ Datasheet - Page 20

• Manufacturer Part Number: ADF4153BRUZ
• Description: IC SYNTH PLL RF F-N FREQ 16TSSOP
• Manufacturer: Analog Devices Inc
• Type: Fractional N Synthesizer (RF)r

Specifications of ADF4153BRUZ

• Pll: Yes
• Input: CMOS
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:1
• Differential - Input:output: Yes/No
• Frequency - Max: 4GHz
• Divider/multiplier: No/Yes
• Voltage - Supply: 2.7 V ~ 3.3 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Frequency-max: 4GHz
• Pll Type: Frequency Synthesis
• Frequency: 4GHz
• Supply Current: 20mA
• Supply Voltage Range: 2.7V To 3.3V
• Digital Ic Case Style: TSSOP
• No. Of Pins: 16
• Operating Temperature Range: -40°C To +85°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADF4153EBZ1 - BOARD EVAL FOR ADF4153
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADF4153
Reference Spurs
Reference spurs are generally not a problem in fractional-N
synthesizers because the reference offset is far outside the
loop bandwidth. However, any reference feedthrough mechan-
ism that bypasses the loop can cause a problem. One such
mechanism is feedthrough of low levels of on-chip reference
switching noise out through the RF
resulting in reference spur levels as high as –90 dBc. Care
should be taken in the PCB layout to ensure that the VCO
is well separated from the input reference to avoid a possible
feed-through path on the board.
SPUR CONSISTENCY
When jumping from Frequency A to Frequency B and then
back again using some fractional-N synthesizers, the spur levels
often differ each time Frequency A is programmed. However,
in the ADF4153, the spur levels on any particular channel are
always consistent.
PHASE RESYNC
The output of a fractional-N PLL can settle to any one of MOD
phase offsets with respect to the input reference, where MOD
is the fractional modulus. The phase resync feature in the
ADF4153 can be used to produce a consistent output phase
offset with respect to the input reference. This is necessary
in applications where the output phase and frequency are
important, such as digital beam-forming.
When phase resync is enabled, an internal timer generates sync
signals at intervals of t
where t
RESYNC is the decimal value programmed in Bits DB[15…12]
of Register R2 and can be any integer in the range of 1 to 15. If
RESYNC is programmed to its default value of all zeros, then
the phase resync feature is disabled.
If phase resync is enabled, then RESYNC_DELAY must be
programmed to a value that is an integer multiple of the value
of MOD. RESYNC_DELAY is the decimal value programmed
into the MOD bits (DB[13…3] of Register R1 when load
control (Bit DB23 of Register R1) = 1.
When a new frequency is programmed, the second next sync
pulse after the LE rising edge is used to resynchronize the output
phase to the reference. The t
a value that is at least as long as the worst-case lock time. Doing
so guarantees that the phase resync occurs after the last cycle
slip in the PLL settling transient.
In the example shown in Figure 17, the PFD reference is
25 MHz and MOD = 125 for a 200 kHz channel spacing.
t
RESYNC_DELAY = 1000.
SYNC
t
is set to 400 μs by programming RESYNC = 10 and
SYNC
PFD
= RESYNC × RESYNC_DELAY × t
is the PFD reference period.
SYNC
given by the following formula:
SYNC
time should be programmed to
IN
pin back to the VCO,
PFD
Rev. D | Page 20 of 24
FILTER DESIGN—ADIsimPLL
A filter design and analysis program is available to help the user
implement PLL design. Visit www.analog.com/pll for a free
download of the ADIsimPLL software. The software designs,
simulates, and analyzes the entire PLL frequency domain and
time domain response. Various passive and active filter
architectures are allowed.
INTERFACING
The ADF4153 has a simple SPI®-compatible serial interface
for writing to the device. CLK, DATA, and LE control the data
transfer. When latch enable (LE) is high, the 22 bits that are
clocked into the input register on each rising edge of SCLK are
transferred to the appropriate latch. See Figure 2 for the timing
diagram and Table 5 for the register truth table.
The maximum allowable serial clock rate is 20 MHz.
ADuC812 Interface
Figure 18 shows the interface between the ADF4153 and the
ADuC812
an 8051 core, this interface can be used with any 8051-based
micro-controller. The MicroConverter is set up for SPI master
mode with CPHA = 0. To initiate the operation, the I/O port
driving LE is brought low. Each latch of the ADF4153 needs a 24-
bit word, which is accomplished by writing three 8-bit bytes from
the MicroConverter to the device. After the third byte is written,
the LE input should be brought high to complete the transfer.
FREQUENCY
(INTERNAL)
PHASE
SYNC
ADuC812
LE
–100
MicroConverter®. Because the ADuC812 is based on
I/O PORTS
SCLOCK
LAST CYCLE SLIP
Figure 18. ADuC812 to ADF4153 Interface
0
MOSI
Figure 17. Phase Resync Example
100
200
INCORRECT PHASE
300
PLL SETTLES TO
t
SYNC
400
TIME (µs)
500
CLK
DATA
LE
MUXOUT
(LOCK DETECT)
600
ADF4153
CORRECT PHASE
PLL SETTLES TO
AFTER RESYNC
700
800
900
1000