ICS85352AYILF IDT, Integrated Device Technology Inc, ICS85352AYILF Datasheet - Page 2

• Manufacturer Part Number: ICS85352AYILF
• Description: IC CLK MUX 2:1 LVPECL 48-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: HiPerClockS™r
• Type: Multiplexerr

Specifications of ICS85352AYILF

• Number Of Circuits: 1
• Ratio - Input:output: 2:12
• Differential - Input:output: Yes/Yes
• Input: HCSL, LVDS, LVHSTL, LVPECL, SSTL
• Output: LVPECL
• Frequency - Max: 700MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP, 48-VQFP
• Frequency-max: 700MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 800-1174; 85352AYILF

ICS85352I Data Sheet
Table 1. Pin Descriptions
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Function Table
Table 3. Control Input Function Table
ICS85352AYI REVISION C AUGUST 3, 2010
Symbol
C
R
R
13, 24, 37, 48
IN
PULLUP
PULLDOWN
Number
16, 17,
18, 19,
20, 21,
40, 41,
42, 43,
11, 12
25, 26
27, 28
29, 30
31, 32
33, 34
35, 36
14, 23
15, 22
44, 45
9, 10
1, 2
3, 4
5, 6
7, 8
38
39
46
47
SELx
0
1
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
SEL10, SEL11,
SEL5, SEL4,
SEL3, SEL9,
SEL8, SEL7,
SEL6, SEL0,
SEL1, SEL2
nQ11, Q11
nQ10, Q10
Q0, nQ0
Q1, nQ1
Q2, nQ2
Q3, nQ3
Q4, nQ4
Q5, nQ5
nQ9, Q9
nQ8, Q8
nQ7, Q7
nQ6, Q6
nCLK1
nCLK0
Name
V
CLK1
CLK0
V
V
CCO
CC
Selected Clock inputs
EE
CLK0, nCLK0
CLK1, nCLK1
Output
Power
Power
Power
Input
Input
Input
Input
Input
Type
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Pullup/
Pullup/
Test Conditions
Description
Differential output pairs. LVPECL interface levels.
Output power supply pins.
Negative power supply pins.
Positive power supply pins.
Clock select inputs. LVCMOS / LVTTL interface levels. See Table 3.
Non-inverting differential clock input.
Inverting differential clock input. V
Non-inverting differential clock input.
Inverting differential clock input. V
2
Minimum
12 BIT, 2-TO-1, 3.3V, 2.5V LVPECL CLOCK BUFFER
CC
CC
/2 default when left floating.
/2 default when left floating
Typical
©2010 Integrated Device Technology, Inc.
51
51
4
Maximum
Units
k
k
pF
Ω
Ω