ICS85352AYILF IDT, Integrated Device Technology Inc, ICS85352AYILF Datasheet - Page 11

• Manufacturer Part Number: ICS85352AYILF
• Description: IC CLK MUX 2:1 LVPECL 48-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: HiPerClockS™r
• Type: Multiplexerr

Specifications of ICS85352AYILF

• Number Of Circuits: 1
• Ratio - Input:output: 2:12
• Differential - Input:output: Yes/Yes
• Input: HCSL, LVDS, LVHSTL, LVPECL, SSTL
• Output: LVPECL
• Frequency - Max: 700MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP, 48-VQFP
• Frequency-max: 700MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 800-1174; 85352AYILF

Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
The differential outputs are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50Ω
Figure 4A. 3.3V LVPECL Output Termination
ICS85352I Data Sheet
ICS85352AYI REVISION C AUGUST 3, 2010
RTT =
((V
3.3V
OH
LVPECL
+ V
OL
) / (V
1
CC
Z
Z
– 2)) – 2
o
o
= 50Ω
= 50Ω
* Z
R1
50Ω
o
RTT
R2
50Ω
V
+
_
CC
3.3V
- 2V
Input
11
transmission lines. Matched impedance techniques should be used
to maximize operating frequency and minimize signal distortion.
Figures 4A and 4B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers simulate
to guarantee compatibility across all printed circuit and clock
component process variations.
Figure 4B. 3.3V LVPECL Output Termination
3.3V
LVPECL
12 BIT, 2-TO-1, 3.3V, 2.5V LVPECL CLOCK BUFFER
Z
Z
o
o
= 50Ω
= 50Ω
R3
125Ω
©2010 Integrated Device Technology, Inc.
R1
84Ω
3.3V
R4
125Ω
R2
84Ω
+
_
3.3V
Input