ICS85408BGLF IDT, Integrated Device Technology Inc, ICS85408BGLF Datasheet - Page 9

• Manufacturer Part Number: ICS85408BGLF
• Description: IC CLK DISTR DIFF-LVDS 24-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: HiPerClockS™r
• Type: Fanout Buffer (Distribution)r

Specifications of ICS85408BGLF

• Number Of Circuits: 1
• Ratio - Input:output: 1:8
• Differential - Input:output: Yes/Yes
• Input: HCSL, LVDS, LVHSTL, LVPECL, SSTL
• Output: LVDS
• Frequency - Max: 700MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP
• Frequency-max: 700MHz
• Number Of Outputs: 16
• Operating Supply Voltage (max): 3.465V
• Operating Temp Range: 0C to 70C
• Propagation Delay Time: 5ns
• Operating Supply Voltage (min): 3.135V
• Mounting: Surface Mount
• Pin Count: 24
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSSOP
• Duty Cycle: 55%
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 800-1182; 800-1182-5; 800-1182; 85408BGLF

ICS85408 Datasheet
Application Information
Wiring the Differential Input to Accept Single-Ended Levels
Figure 1 shows how the differential input can be wired to accept
single-ended levels. The reference voltage V_REF = V
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the
center of the input voltage swing. For example, if the input clock swing
is only 2.5V and V
0.609.
Recommendations for Unused Output Pins
Outputs:
LVDS Outputs
All unused LVDS output pairs can be either left floating or terminated
with 100Ω across. If they are left floating, there should be no trace
attached.
ICS85408BG REVISION B JUNE 25, 2009
DD
= 3.3V, V_REF should be 1.25V and R2/R1 =
DD
/2 is
9
Figure 1. Single-Ended Signal Driving Differential Input
Single Ended Clock Input
LOW SKEW, 1-TO-8, DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
C1
0.1u
V_REF
R1
1K
R2
1K
V
DD
©2009 Integrated Device Technology, Inc.
CLK
nCLK